A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon

Yun Kwon Park; Yong Kook Kim; Hoon Kim; Duck Jung Lee; Chul Ju Kim; Byeong Kwon Ju; Jong Oh Park

A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon

Yun Kwon Park, Yong Kook Kim, Hoon Kim, Duck Jung Lee, Chul Ju Kim, Byeong Kwon Ju, Jong Oh Park

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper, as ultra thin silicon substrate was used as packaging substrate, we proposed ultra thin chip size RF-MEMS packaging technology that has vertical feed-through for low loss, as reduced the parasitic capacity. Thin silicon wafer with 50um thickness was fabricated to achieve short electric path, low loss and lightweight. And then via holes with the diameter of 60um were fabricated and was filled by the RIE and electroplating process. Also, the wafer level bumps were fabricated for simple, low cost, and fine patterning process. The measured S-parameter of packaged CPW(Co-planner waveguide) has the reflection loss of under -19 dB and the insertion loss of -0.54 -0.67 dB.

Original language	English
Pages	618-621
Number of pages	4
Publication status	Published - 2003
Externally published	Yes
Event	IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems - Kyoto, Japan Duration: 2003 Jan 19 → 2003 Jan 23

Other

Other	IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems
Country/Territory	Japan
City	Kyoto
Period	03/1/19 → 03/1/23

ASJC Scopus subject areas

Control and Systems Engineering
Mechanical Engineering
Electrical and Electronic Engineering

Cite this

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title = "A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon",

abstract = "In this paper, as ultra thin silicon substrate was used as packaging substrate, we proposed ultra thin chip size RF-MEMS packaging technology that has vertical feed-through for low loss, as reduced the parasitic capacity. Thin silicon wafer with 50um thickness was fabricated to achieve short electric path, low loss and lightweight. And then via holes with the diameter of 60um were fabricated and was filled by the RIE and electroplating process. Also, the wafer level bumps were fabricated for simple, low cost, and fine patterning process. The measured S-parameter of packaged CPW(Co-planner waveguide) has the reflection loss of under -19 dB and the insertion loss of -0.54 -0.67 dB.",

author = "Park, {Yun Kwon} and Kim, {Yong Kook} and Hoon Kim and Lee, {Duck Jung} and Kim, {Chul Ju} and Ju, {Byeong Kwon} and Park, {Jong Oh}",

year = "2003",

language = "English",

pages = "618--621",

note = "IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems ; Conference date: 19-01-2003 Through 23-01-2003",

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TY - CONF

T1 - A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon

AU - Park, Yun Kwon

AU - Kim, Yong Kook

AU - Kim, Hoon

AU - Lee, Duck Jung

AU - Kim, Chul Ju

AU - Ju, Byeong Kwon

AU - Park, Jong Oh

PY - 2003

Y1 - 2003

N2 - In this paper, as ultra thin silicon substrate was used as packaging substrate, we proposed ultra thin chip size RF-MEMS packaging technology that has vertical feed-through for low loss, as reduced the parasitic capacity. Thin silicon wafer with 50um thickness was fabricated to achieve short electric path, low loss and lightweight. And then via holes with the diameter of 60um were fabricated and was filled by the RIE and electroplating process. Also, the wafer level bumps were fabricated for simple, low cost, and fine patterning process. The measured S-parameter of packaged CPW(Co-planner waveguide) has the reflection loss of under -19 dB and the insertion loss of -0.54 -0.67 dB.

AB - In this paper, as ultra thin silicon substrate was used as packaging substrate, we proposed ultra thin chip size RF-MEMS packaging technology that has vertical feed-through for low loss, as reduced the parasitic capacity. Thin silicon wafer with 50um thickness was fabricated to achieve short electric path, low loss and lightweight. And then via holes with the diameter of 60um were fabricated and was filled by the RIE and electroplating process. Also, the wafer level bumps were fabricated for simple, low cost, and fine patterning process. The measured S-parameter of packaged CPW(Co-planner waveguide) has the reflection loss of under -19 dB and the insertion loss of -0.54 -0.67 dB.

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UR - http://www.scopus.com/inward/citedby.url?scp=0038494016&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0038494016

SP - 618

EP - 621

T2 - IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems

Y2 - 19 January 2003 through 23 January 2003

ER -

A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon

Abstract

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ASJC Scopus subject areas

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