Abstract
This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at VDD = 0.9 V.
Original language | English |
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Article number | 9132691 |
Pages (from-to) | 1264-1268 |
Number of pages | 5 |
Journal | IEEE Transactions on Power Electronics |
Volume | 36 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2021 Feb |
Keywords
- Capacitively coupled level shifter (LS)
- conditional switching signal
- nonperiodic signal
- periodic charge refresh
ASJC Scopus subject areas
- Electrical and Electronic Engineering