Abstract
This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at VDD = 0.9 V.
| Original language | English |
|---|---|
| Article number | 9132691 |
| Pages (from-to) | 1264-1268 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Power Electronics |
| Volume | 36 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2021 Feb |
Bibliographical note
Funding Information:Manuscript received May 15, 2020; revised June 12, 2020; accepted June 28, 2020. Date of publication July 2, 2020; date of current version September 22, 2020. This work was supported by the Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea Government (MSIT) (2019-0-01370, Development of LPDDR5 memory interface for A.I. application processor). (Corresponding author: Chulwoo Kim.) Junyoung Maeng, Inho Park, and Chulwoo Kim are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]; [email protected]).
Publisher Copyright:
© 1986-2012 IEEE.
Keywords
- Capacitively coupled level shifter (LS)
- conditional switching signal
- nonperiodic signal
- periodic charge refresh
ASJC Scopus subject areas
- Electrical and Electronic Engineering
