A Periodically Refreshed Capacitive Floating Level Shifter for Conditional Switching Applications

Junyoung Maeng; Minseob Shim; Junwon Jeong; Inho Park; Chulwoo Kim

doi:10.1109/TPEL.2020.3006615

A Periodically Refreshed Capacitive Floating Level Shifter for Conditional Switching Applications

Junyoung Maeng
, Minseob Shim
, Junwon Jeong
, Inho Park
, Chulwoo Kim^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at VDD = 0.9 V.

Original language	English
Article number	9132691
Pages (from-to)	1264-1268
Number of pages	5
Journal	IEEE Transactions on Power Electronics
Volume	36
Issue number	2
DOIs	https://doi.org/10.1109/TPEL.2020.3006615
Publication status	Published - 2021 Feb

Bibliographical note

Funding Information:
Manuscript received May 15, 2020; revised June 12, 2020; accepted June 28, 2020. Date of publication July 2, 2020; date of current version September 22, 2020. This work was supported by the Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea Government (MSIT) (2019-0-01370, Development of LPDDR5 memory interface for A.I. application processor). (Corresponding author: Chulwoo Kim.) Junyoung Maeng, Inho Park, and Chulwoo Kim are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]; [email protected]).

Publisher Copyright:
© 1986-2012 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Capacitively coupled level shifter (LS)
conditional switching signal
nonperiodic signal
periodic charge refresh

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TPEL.2020.3006615

Cite this

@article{639a9993ee8e4cf3a8a9a1ea2a093934,

title = "A Periodically Refreshed Capacitive Floating Level Shifter for Conditional Switching Applications",

abstract = "This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at VDD = 0.9 V.",

keywords = "Capacitively coupled level shifter (LS), conditional switching signal, nonperiodic signal, periodic charge refresh",

author = "Junyoung Maeng and Minseob Shim and Junwon Jeong and Inho Park and Chulwoo Kim",

note = "Funding Information: Manuscript received May 15, 2020; revised June 12, 2020; accepted June 28, 2020. Date of publication July 2, 2020; date of current version September 22, 2020. This work was supported by the Institute of Information \& communications Technology Planning \& Evaluation (IITP) grant funded by the Korea Government (MSIT) (2019-0-01370, Development of LPDDR5 memory interface for A.I. application processor). (Corresponding author: Chulwoo Kim.) Junyoung Maeng, Inho Park, and Chulwoo Kim are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]; [email protected]). Publisher Copyright: {\textcopyright} 1986-2012 IEEE.",

year = "2021",

month = feb,

doi = "10.1109/TPEL.2020.3006615",

language = "English",

volume = "36",

pages = "1264--1268",

journal = "IEEE Transactions on Power Electronics",

issn = "0885-8993",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - A Periodically Refreshed Capacitive Floating Level Shifter for Conditional Switching Applications

AU - Maeng, Junyoung

AU - Shim, Minseob

AU - Jeong, Junwon

AU - Park, Inho

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received May 15, 2020; revised June 12, 2020; accepted June 28, 2020. Date of publication July 2, 2020; date of current version September 22, 2020. This work was supported by the Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea Government (MSIT) (2019-0-01370, Development of LPDDR5 memory interface for A.I. application processor). (Corresponding author: Chulwoo Kim.) Junyoung Maeng, Inho Park, and Chulwoo Kim are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]; [email protected]). Publisher Copyright: © 1986-2012 IEEE.

PY - 2021/2

Y1 - 2021/2

N2 - This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at VDD = 0.9 V.

AB - This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at VDD = 0.9 V.

KW - Capacitively coupled level shifter (LS)

KW - conditional switching signal

KW - nonperiodic signal

KW - periodic charge refresh

UR - https://www.scopus.com/pages/publications/85092593313

U2 - 10.1109/TPEL.2020.3006615

DO - 10.1109/TPEL.2020.3006615

M3 - Article

AN - SCOPUS:85092593313

SN - 0885-8993

VL - 36

SP - 1264

EP - 1268

JO - IEEE Transactions on Power Electronics

JF - IEEE Transactions on Power Electronics

IS - 2

M1 - 9132691

ER -

A Periodically Refreshed Capacitive Floating Level Shifter for Conditional Switching Applications

Abstract

Bibliographical note

UN SDGs

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this