A Perspective on Test Methodologies for Supervised Machine Learning Accelerators

Seyedhamidreza Motaman; Swaroop Ghosh; Jongsun Park

doi:10.1109/JETCAS.2019.2933678

A Perspective on Test Methodologies for Supervised Machine Learning Accelerators

Seyedhamidreza Motaman, Swaroop Ghosh, Jongsun Park

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

Neural Network (NN) accelerators are essential in many emerging applications e.g., autonomous systems in making mission-critical decisions, health-care solutions to assist with diagnoses, etc. Any soft or hard failure during operation can potentially have catastrophic consequences in many of these applications. For instance, inaccurate classification during object recognition and tracking in autonomous vehicles can lead to crashes and subsequent injuries to the passengers. Therefore, testing Neural Network accelerators to ensure reliability and integrity of the underlying hardware is a crucial task to ensure the functionality, especially the ones that are used in mission-critical applications. Conventional functional, stuck-at and delay tests are not sufficient to characterize the ML systems since they face new test and validation challenges. This paper is aimed to provide a perspective on new test requirements and design for test techniques to cover ML features and detect various type of faults in NN accelerator. We discuss First-In-First-Out (FIFO) and Scratchpad based neural network hardware accelerators and propose test methods to detect the faults as well as fault location in different modules of the accelerator including MAC unit, Activation function module, and Processing Element (PE) registers.

Original language	English
Article number	8790753
Pages (from-to)	562-569
Number of pages	8
Journal	IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Volume	9
Issue number	3
DOIs	https://doi.org/10.1109/JETCAS.2019.2933678
Publication status	Published - 2019 Sept

Bibliographical note

Funding Information:
Manuscript received May 6, 2019; revised July 19, 2019; accepted August 2, 2019. Date of publication August 7, 2019; date of current version September 17, 2019. 2019. This work was supported in part by the Semiconductor Research Corporation under Grant 2847.001, in part by NSF under Grant CNS-1722557, Grant CNS-1814710, Grant CCF-1718474, Grant DGE-1723687, and Grant DGE-1821766, in part by the DARPA Young Faculty Award under Grant D15AP00089, and in part by the Industrial Strategic Technology Development Program under Grant 10077445. This article was recommended by Guest Editor R. Joshi. (Corresponding author: Seyedhamidreza Motaman.) S. Motaman is with Intel Inc., Santa Clara, CA 95054 USA (e-mail: [email protected]).

Publisher Copyright:
© 2011 IEEE.

Keywords

DFT
hardware accelerator
neural network
stuck at fault

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JETCAS.2019.2933678

Cite this

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abstract = "Neural Network (NN) accelerators are essential in many emerging applications e.g., autonomous systems in making mission-critical decisions, health-care solutions to assist with diagnoses, etc. Any soft or hard failure during operation can potentially have catastrophic consequences in many of these applications. For instance, inaccurate classification during object recognition and tracking in autonomous vehicles can lead to crashes and subsequent injuries to the passengers. Therefore, testing Neural Network accelerators to ensure reliability and integrity of the underlying hardware is a crucial task to ensure the functionality, especially the ones that are used in mission-critical applications. Conventional functional, stuck-at and delay tests are not sufficient to characterize the ML systems since they face new test and validation challenges. This paper is aimed to provide a perspective on new test requirements and design for test techniques to cover ML features and detect various type of faults in NN accelerator. We discuss First-In-First-Out (FIFO) and Scratchpad based neural network hardware accelerators and propose test methods to detect the faults as well as fault location in different modules of the accelerator including MAC unit, Activation function module, and Processing Element (PE) registers.",

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note = "Funding Information: Manuscript received May 6, 2019; revised July 19, 2019; accepted August 2, 2019. Date of publication August 7, 2019; date of current version September 17, 2019. 2019. This work was supported in part by the Semiconductor Research Corporation under Grant 2847.001, in part by NSF under Grant CNS-1722557, Grant CNS-1814710, Grant CCF-1718474, Grant DGE-1723687, and Grant DGE-1821766, in part by the DARPA Young Faculty Award under Grant D15AP00089, and in part by the Industrial Strategic Technology Development Program under Grant 10077445. This article was recommended by Guest Editor R. Joshi. (Corresponding author: Seyedhamidreza Motaman.) S. Motaman is with Intel Inc., Santa Clara, CA 95054 USA (e-mail: [email protected]). Publisher Copyright: {\textcopyright} 2011 IEEE.",

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A Perspective on Test Methodologies for Supervised Machine Learning Accelerators

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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