A piecewise linear 10 bit DAC architecture with drain current modulation for compact LCD driver ICs

Yong Joon Jeon; Hyung Min Lee; Sung Woo Lee; Gyu Hyeong Cho; Hyoung Rae Kim; Yoon Kyung Choi; Myunghee Lee

doi:10.1109/JSSC.2009.2035547

A piecewise linear 10 bit DAC architecture with drain current modulation for compact LCD driver ICs

Yong Joon Jeon^*
, Hyung Min Lee
, Sung Woo Lee
, Gyu Hyeong Cho
, Hyoung Rae Kim
, Yoon Kyung Choi
, Myunghee Lee

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

36 Citations (Scopus)

Abstract

A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC.

Original language	English
Article number	5342341
Pages (from-to)	3659-3675
Number of pages	17
Journal	IEEE Journal of Solid-State Circuits
Volume	44
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2009.2035547
Publication status	Published - 2009 Dec
Externally published	Yes

Bibliographical note

Funding Information:
Manuscript received April 27, 2009; revised August 18, 2009. Current version published December 11, 2009. This paper was approved by Guest Editor Roland Thewes. This work was supported by the ERC program of the Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea Ministry of Science and Technology (MOST) (No. R11-2007-045-01004-0).

Copyright:
Copyright 2010 Elsevier B.V., All rights reserved.

Keywords

Cascaded-dividing DAC
Data driver
Drain current modulation
Interpolation
LCD
Piecewise linear

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2009.2035547

Cite this

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title = "A piecewise linear 10 bit DAC architecture with drain current modulation for compact LCD driver ICs",

abstract = "A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2\% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC.",

keywords = "Cascaded-dividing DAC, Data driver, Drain current modulation, Interpolation, LCD, Piecewise linear",

author = "Jeon, \{Yong Joon\} and Lee, \{Hyung Min\} and Lee, \{Sung Woo\} and Cho, \{Gyu Hyeong\} and Kim, \{Hyoung Rae\} and Choi, \{Yoon Kyung\} and Myunghee Lee",

note = "Funding Information: Manuscript received April 27, 2009; revised August 18, 2009. Current version published December 11, 2009. This paper was approved by Guest Editor Roland Thewes. This work was supported by the ERC program of the Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea Ministry of Science and Technology (MOST) (No. R11-2007-045-01004-0). Copyright: Copyright 2010 Elsevier B.V., All rights reserved.",

year = "2009",

month = dec,

doi = "10.1109/JSSC.2009.2035547",

language = "English",

volume = "44",

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AU - Kim, Hyoung Rae

AU - Choi, Yoon Kyung

AU - Lee, Myunghee

N1 - Funding Information: Manuscript received April 27, 2009; revised August 18, 2009. Current version published December 11, 2009. This paper was approved by Guest Editor Roland Thewes. This work was supported by the ERC program of the Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea Ministry of Science and Technology (MOST) (No. R11-2007-045-01004-0). Copyright: Copyright 2010 Elsevier B.V., All rights reserved.

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N2 - A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC.

AB - A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC.

KW - Cascaded-dividing DAC

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KW - Drain current modulation

KW - Interpolation

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KW - Piecewise linear

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ER -

A piecewise linear 10 bit DAC architecture with drain current modulation for compact LCD driver ICs

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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