A Pre-charge based Data Cell Dynamic Reference Sensing Scheme for Reliable Read Operations in STT-MRAM

Although spin transfer torque magnetic random access memory (STT-MRAM) has emerged as a strong candidate to replace conventional memories, relatively small read margin caused by low tunnel magnetoresistance (TMR) with process variations remains a significant challenge. In this paper, we present a data cell dynamic reference (DCDR) sensing scheme that significantly improves the sensing margin by comparing the parallel (P) and antiparallel (AP) states of the memory cells, rather than using an intermediate reference cell. This approach leverages a signal generator unit and a sample & hold circuit to efficiently manage the reference voltage, ensuring that the sensing operation fully reflects the difference between P and AP states. Simulations using 28nm CMOS technology with a 256Χ256 array demonstrate that the proposed DCDR approach achieves a sensing margin up to 257mV under a bit-error-rate (BER) of 7.99E-8 at 1.21ns, which represents a 2x larger margin and more than 100 times lower BER compared to the conventional scheme. By scaling down the precharge voltage, the proposed scheme results in over 30% read energy savings and 45% faster read speed under ISO 1E-5 target BER condition.