Abstract
The keys to good signal integrity in a Graphic DDR3 (GDDR3) SDRAM interface for a bandwidth up to 1.4Gbps/pin are the minimization of input/output pin capacitance and the accurate control of the output data skew. The proposed pre-emphasis output buffer control scheme provides output data skew minimization without an increase of input/output pin capacitance. Compared to the conventional scheme, the output data aperture window of proposed scheme has increased by 18% and the data output skew has decreased by 48%.
Original language | English |
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Pages (from-to) | 446-451 |
Number of pages | 6 |
Journal | ieice electronics express |
Volume | 5 |
Issue number | 12 |
DOIs | |
Publication status | Published - 2008 Jun 25 |
Keywords
- GDDR3 SDRAM
- Signal integrity
- Termination
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering