Abstract
This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.
Original language | English |
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Article number | 3069 |
Journal | Electronics (Switzerland) |
Volume | 12 |
Issue number | 14 |
DOIs | |
Publication status | Published - 2023 Jul |
Bibliographical note
Publisher Copyright:© 2023 by the authors.
Keywords
- CMOS
- Q-band receiver
- down-conversion mixer
- frequency divider
- image rejection
- low-noise amplifier
- voltage-controlled oscillator
ASJC Scopus subject areas
- Control and Systems Engineering
- Signal Processing
- Hardware and Architecture
- Computer Networks and Communications
- Electrical and Electronic Engineering