Abstract
A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies 0.25 mm2.
Original language | English |
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Pages (from-to) | 378-386 |
Number of pages | 9 |
Journal | Journal of Semiconductor Technology and Science |
Volume | 17 |
Issue number | 3 |
DOIs | |
Publication status | Published - 2017 |
Bibliographical note
Funding Information:This work was supported by the IT R&D program of MOTIE/KEIT. [10054819, Development of modular wearable platform technology for the disaster and industrial site]. It was also partially supported by the Chung-Ang University Excellent Student Scholarship in 2015.
Publisher Copyright:
© 2017, Institute of Electronics Engineers of Korea. All rights reserved.
Keywords
- Digital-to-analog converter (DAC)
- Return-to-zero (RZ)
- Tri-state switching scheme
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering