TY - JOUR
T1 - A Scalable 300-GHz Multichip Stitched CMOS Detector Array
AU - Song, Kiryong
AU - Kim, Doyoon
AU - Kim, Jungsoo
AU - Yoo, Junghwan
AU - Keum, Wooyong
AU - Rieh, Jae Sung
N1 - Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government under Grant NRF-2021R1A2C3009096
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2022/3/1
Y1 - 2022/3/1
N2 - A terahertz (THz) CMOS detector array based on multiple chips stitched together is reported. The proposed multichip detector is scalable as the total number of subarray chips is flexible and can be controlled as needed with the help of the modular scheme adopted. Based on the presented multichip technique, a 3× 3 multichip detector array composed of nine subarray chips has been implemented in this work for operation at 300 GHz. With the subarray chips, each with 7× 7 pixels, the complete multichip array comprises 21 ×21 physical pixels. By employing virtual pixels, which are included to compensate for the chip interface area consumed for interchip wire-bonding in this work, THz real-time images with 23×23 pixels have been successfully acquired. The distribution of the responsivity and noise equivalent power (NEP) over the multichip array is presented. The responsivity distribution shows the effect of the series resistance of the long bias lines stretched over the multichip array, while the effect is not apparent for NEP. The distribution due to series resistance, as well as other nonuniformities over the pixels and chips due to various causes, can be suppressed with a proper calibration for the images acquired with the multichip array.
AB - A terahertz (THz) CMOS detector array based on multiple chips stitched together is reported. The proposed multichip detector is scalable as the total number of subarray chips is flexible and can be controlled as needed with the help of the modular scheme adopted. Based on the presented multichip technique, a 3× 3 multichip detector array composed of nine subarray chips has been implemented in this work for operation at 300 GHz. With the subarray chips, each with 7× 7 pixels, the complete multichip array comprises 21 ×21 physical pixels. By employing virtual pixels, which are included to compensate for the chip interface area consumed for interchip wire-bonding in this work, THz real-time images with 23×23 pixels have been successfully acquired. The distribution of the responsivity and noise equivalent power (NEP) over the multichip array is presented. The responsivity distribution shows the effect of the series resistance of the long bias lines stretched over the multichip array, while the effect is not apparent for NEP. The distribution due to series resistance, as well as other nonuniformities over the pixels and chips due to various causes, can be suppressed with a proper calibration for the images acquired with the multichip array.
KW - CMOS integrated circuits
KW - Imaging
KW - Semiconductor detectors
KW - Sensor arrays
UR - http://www.scopus.com/inward/record.url?scp=85117300882&partnerID=8YFLogxK
U2 - 10.1109/TMTT.2021.3118305
DO - 10.1109/TMTT.2021.3118305
M3 - Article
AN - SCOPUS:85117300882
SN - 0018-9480
VL - 70
SP - 1797
EP - 1809
JO - IEEE Transactions on Microwave Theory and Techniques
JF - IEEE Transactions on Microwave Theory and Techniques
IS - 3
ER -