A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS

Sanggeun Jeon; Yu Jiu Wang; Hua Wang; Florian Bohn; Arun Natarajan; Aydin Babakhani; Ali Hajimiri

doi:10.1109/ISSCC.2008.4523119

A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS

Sanggeun Jeon, Yu Jiu Wang, Hua Wang, Florian Bohn, Arun Natarajan, Aydin Babakhani, Ali Hajimiri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

A 6-to-18GHz integrated phased-array receiver is implemented in 0.13μm CMOS and is designed for scalability to very large arrays. It concurrently forms four beams at two different frequencies between 6 and 18GHz. Each receiver element achieves worst-case cross-polarization and cross-band rejections of 63.4dB and 48.8dB, respectively, over the entire band. A four-element phased array provides array patterns with peak-to-null ratio of 23dB and total array gain of 27.7dB at 18GHz.

Original language	English
Title of host publication	2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	186-188
Number of pages	3
ISBN (Print)	9781424420100
DOIs	https://doi.org/10.1109/ISSCC.2008.4523119
Publication status	Published - 2008
Externally published	Yes
Event	2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2008 Feb 3 → 2008 Feb 7

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	51
ISSN (Print)	0193-6530

Other

Other	2008 IEEE International Solid State Circuits Conference, ISSCC
Country/Territory	United States
City	San Francisco, CA
Period	08/2/3 → 08/2/7

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2008.4523119

Cite this

Jeon, S., Wang, Y. J., Wang, H., Bohn, F., Natarajan, A., Babakhani, A., & Hajimiri, A. (2008). A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC (pp. 186-188). Article 4523119 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2008.4523119

A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS. / Jeon, Sanggeun; Wang, Yu Jiu; Wang, Hua et al.
2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc., 2008. p. 186-188 4523119 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jeon, S, Wang, YJ, Wang, H, Bohn, F, Natarajan, A, Babakhani, A & Hajimiri, A 2008, A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS. in 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC., 4523119, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 51, Institute of Electrical and Electronics Engineers Inc., pp. 186-188, 2008 IEEE International Solid State Circuits Conference, ISSCC, San Francisco, CA, United States, 08/2/3. https://doi.org/10.1109/ISSCC.2008.4523119

Jeon S, Wang YJ, Wang H, Bohn F, Natarajan A, Babakhani A et al. A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc. 2008. p. 186-188. 4523119. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2008.4523119

Jeon, Sanggeun ; Wang, Yu Jiu ; Wang, Hua et al. / A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS. 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc., 2008. pp. 186-188 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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abstract = "A 6-to-18GHz integrated phased-array receiver is implemented in 0.13μm CMOS and is designed for scalability to very large arrays. It concurrently forms four beams at two different frequencies between 6 and 18GHz. Each receiver element achieves worst-case cross-polarization and cross-band rejections of 63.4dB and 48.8dB, respectively, over the entire band. A four-element phased array provides array patterns with peak-to-null ratio of 23dB and total array gain of 27.7dB at 18GHz.",

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AB - A 6-to-18GHz integrated phased-array receiver is implemented in 0.13μm CMOS and is designed for scalability to very large arrays. It concurrently forms four beams at two different frequencies between 6 and 18GHz. Each receiver element achieves worst-case cross-polarization and cross-band rejections of 63.4dB and 48.8dB, respectively, over the entire band. A four-element phased array provides array patterns with peak-to-null ratio of 23dB and total array gain of 27.7dB at 18GHz.

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A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS

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