TY - GEN
T1 - A scalable 6-to-18GHz concurrent dual-band quad-beam phased-array receiver in CMOS
AU - Jeon, Sanggeun
AU - Wang, Yu Jiu
AU - Wang, Hua
AU - Bohn, Florian
AU - Natarajan, Arun
AU - Babakhani, Aydin
AU - Hajimiri, Ali
PY - 2008
Y1 - 2008
N2 - A 6-to-18GHz integrated phased-array receiver is implemented in 0.13μm CMOS and is designed for scalability to very large arrays. It concurrently forms four beams at two different frequencies between 6 and 18GHz. Each receiver element achieves worst-case cross-polarization and cross-band rejections of 63.4dB and 48.8dB, respectively, over the entire band. A four-element phased array provides array patterns with peak-to-null ratio of 23dB and total array gain of 27.7dB at 18GHz.
AB - A 6-to-18GHz integrated phased-array receiver is implemented in 0.13μm CMOS and is designed for scalability to very large arrays. It concurrently forms four beams at two different frequencies between 6 and 18GHz. Each receiver element achieves worst-case cross-polarization and cross-band rejections of 63.4dB and 48.8dB, respectively, over the entire band. A four-element phased array provides array patterns with peak-to-null ratio of 23dB and total array gain of 27.7dB at 18GHz.
UR - http://www.scopus.com/inward/record.url?scp=49549100026&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2008.4523119
DO - 10.1109/ISSCC.2008.4523119
M3 - Conference contribution
AN - SCOPUS:49549100026
SN - 9781424420100
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 186
EP - 188
BT - 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2008 IEEE International Solid State Circuits Conference, ISSCC
Y2 - 3 February 2008 through 7 February 2008
ER -