A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs

Yunsoo Park, Jintae Kim, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

32 Citations (Scopus)


This paper presents a foreground calibration method for both a sampler and a track-and-hold (T/H) buffer bandwidth mismatch in highly time-interleaved analog-to-digital converters (TI-ADCs). The T/H buffer bandwidth mismatch stems from the length difference of interconnect lines between the buffer and the channel ADC, while the sampler bandwidth mismatch arises from the mismatch in a switch and a sampling capacitor. To address both mismatches along with other mismatches residing in TI-ADCs, this papers utilizes least-squares (LS) minimization technique in order to extract mismatch parameters while injecting a sinewave at two distinct frequencies. Programmable capacitor arrays (PCAs) are used to tune the bandwidth of sampler, and correcting buffer bandwidth mismatch is performed in digital-domain. The method presented here is scalable to arbitrary number of interleaved paths, and can easily be combined with existing calibration methods for gain, offset, and timing-skew mismatches. Numerical experiment via Monte-Carlo simulations demonstrates significant performance improvement in the spurious-free dynamic range (SFDR) from 38 dB to 75 dB for a 32-channel time-interleaved ADC model that includes all major mismatches.

Original languageEnglish
Article number7676404
Pages (from-to)1889-1897
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number11
Publication statusPublished - 2016 Nov


  • Analog-to-digital conversion
  • bandwidth mismatch
  • channel mismatch
  • time-interleaved analog-to-digital converters (TI-ADCs) calibration

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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