A self-calibrated DLL-based clock generator for an energy-aware EISC processor

Sewook Hwang, Kyeong Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)


This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5$\times$ to 8$\times$ of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-$\mu$m CMOS process occupies an active area of 0.27 mm$2 and consumes 15.56 mA.

Original languageEnglish
Article number6175980
Pages (from-to)575-579
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
Publication statusPublished - 2013


  • Calibration
  • delay-locked loop (DLL)
  • dynamic frequency scaling (DFS)
  • extendable instruction set computing (EISC)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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