A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

Dae Young Jeon; So Jeong Park; Mireille Mouis; Sylvain Barraud; Gyu Tae Kim; Gerard Ghibaudo

doi:10.1109/LED.2018.2857623

A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

Dae Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu Tae Kim, Gerard Ghibaudo

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Junctionless transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of \text{t}={\mathrm {si}} from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted \text{t}={\mathrm {si}} values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.

Original language	English
Article number	8413132
Pages (from-to)	1282-1285
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	39
Issue number	9
DOIs	https://doi.org/10.1109/LED.2018.2857623
Publication status	Published - 2018 Sept

Keywords

Junctionless transistors (JLTs)
Si thickness (tsi)
bulk neutral channel
method for parameter extraction
numerical simulation
surface accumulation channel

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2018.2857623

Cite this

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title = "A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors",

abstract = "Junctionless transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of \text{t}={\mathrm {si}} from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted \text{t}={\mathrm {si}} values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.",

keywords = "Junctionless transistors (JLTs), Si thickness (tsi), bulk neutral channel, method for parameter extraction, numerical simulation, surface accumulation channel",

author = "Jeon, {Dae Young} and Park, {So Jeong} and Mireille Mouis and Sylvain Barraud and Kim, {Gyu Tae} and Gerard Ghibaudo",

note = "Funding Information: Manuscript received June 25, 2018; revised July 9, 2018 and July 16, 2018; accepted July 17, 2018. Date of publication July 19, 2018; date of current version August 23, 2018. This work was supported in part by the European Union 7th Framework Program Project SQWIRE under Grant 257111, in part by the Korea Institute of Science and Technology (KIST) Institutional Program, in part by the National Research Foundation of Korea under Grants NRF-2016R1A6A3A11933511, NRF-2017M3D9A1073924, and NRF-2017M3A7B4049167, and in part by the Korea University Grant. The review of this letter was arranged by Editor K. J. Kuhn. (Corresponding author: Dae-Young Jeon.) D.-Y. Jeon is with the Institute of Advanced Composite Materials, Korea Institute of Science and Technology, Jeonbuk 55324, South Korea (e-mail: dyjeon@kist.re.kr). Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",

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doi = "10.1109/LED.2018.2857623",

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AU - Kim, Gyu Tae

AU - Ghibaudo, Gerard

N1 - Funding Information: Manuscript received June 25, 2018; revised July 9, 2018 and July 16, 2018; accepted July 17, 2018. Date of publication July 19, 2018; date of current version August 23, 2018. This work was supported in part by the European Union 7th Framework Program Project SQWIRE under Grant 257111, in part by the Korea Institute of Science and Technology (KIST) Institutional Program, in part by the National Research Foundation of Korea under Grants NRF-2016R1A6A3A11933511, NRF-2017M3D9A1073924, and NRF-2017M3A7B4049167, and in part by the Korea University Grant. The review of this letter was arranged by Editor K. J. Kuhn. (Corresponding author: Dae-Young Jeon.) D.-Y. Jeon is with the Institute of Advanced Composite Materials, Korea Institute of Science and Technology, Jeonbuk 55324, South Korea (e-mail: dyjeon@kist.re.kr). Publisher Copyright: © 1980-2012 IEEE.

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AB - Junctionless transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of \text{t}={\mathrm {si}} from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted \text{t}={\mathrm {si}} values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.

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A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

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