Abstract
Junctionless transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of \text{t}={\mathrm {si}} from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted \text{t}={\mathrm {si}} values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.
Original language | English |
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Article number | 8413132 |
Pages (from-to) | 1282-1285 |
Number of pages | 4 |
Journal | IEEE Electron Device Letters |
Volume | 39 |
Issue number | 9 |
DOIs | |
Publication status | Published - 2018 Sept |
Keywords
- Junctionless transistors (JLTs)
- Si thickness (tsi)
- bulk neutral channel
- method for parameter extraction
- numerical simulation
- surface accumulation channel
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering