A SPICE model of p-channel silicon tunneling field-effect transistors for logic applications

Sola Woo; Juhee Jeon; Sangsig Kim

doi:10.1002/jnm.2793

A SPICE model of p-channel silicon tunneling field-effect transistors for logic applications

Sola Woo, Juhee Jeon, Sangsig Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this study, we propose a SPICE model of p-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at V_DD as low as 0.3 V and that c-TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.

Original language	English
Article number	e2793
Journal	International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Volume	34
Issue number	1
DOIs	https://doi.org/10.1002/jnm.2793
Publication status	Published - 2021 Jan 1

Keywords

SPICE model
TCAD simulation
device modeling
tunnel FET
tunnel FET logic gate

ASJC Scopus subject areas

Modelling and Simulation
Computer Science Applications
Electrical and Electronic Engineering

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10.1002/jnm.2793

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title = "A SPICE model of p-channel silicon tunneling field-effect transistors for logic applications",

abstract = "In this study, we propose a SPICE model of p-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at VDD as low as 0.3 V and that c-TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.",

keywords = "SPICE model, TCAD simulation, device modeling, tunnel FET, tunnel FET logic gate",

author = "Sola Woo and Juhee Jeon and Sangsig Kim",

note = "Funding Information: This research was partly supported by the MOTIE (Ministry of Trade, Industry & Energy) (10067791) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device, the Brain Korea 21 Plus Project in 2020, and Samsung electronics. Publisher Copyright: {\textcopyright} 2020 John Wiley & Sons, Ltd Copyright: Copyright 2020 Elsevier B.V., All rights reserved.",

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PY - 2021/1/1

Y1 - 2021/1/1

N2 - In this study, we propose a SPICE model of p-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at VDD as low as 0.3 V and that c-TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.

AB - In this study, we propose a SPICE model of p-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at VDD as low as 0.3 V and that c-TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.

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KW - TCAD simulation

KW - device modeling

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KW - tunnel FET logic gate

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A SPICE model of p-channel silicon tunneling field-effect transistors for logic applications

Abstract

Keywords

ASJC Scopus subject areas

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