TY - JOUR
T1 - A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays with Fully Integrated 7.2-pF Total Capacitance
AU - Maeng, Junyoung
AU - Shim, Minseob
AU - Jeong, Junwon
AU - Park, Inho
AU - Park, Yunsoo
AU - Kim, Chulwoo
N1 - Funding Information:
Manuscript received June 17, 2019; revised September 18, 2019; accepted October 31, 2019. Date of publication November 19, 2019; date of current version May 27, 2020. This paper was approved by Associate Editor Wing-Hung Ki. This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korea Government (MSIT) under Grant 2019R1A2B5B03100756. (Corresponding author: Chulwoo Kim.) J. Maeng is with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: mjy@kilby.korea.ac.kr).
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2020/6/1
Y1 - 2020/6/1
N2 - A digital low-dropout (DLDO) regulator using p-type MOS (PMOS) and n-type MOS (NMOS) switches is proposed to achieve a sub-fs speed figure-of-merit (FoM) by reducing the total capacitance ( C_{\mathrm {TOT}} ) and accomplishing a comparable output voltage droop ( \Delta V_{\mathrm {OUT}} ) during a load transition. The proposed DLDO uses the segmented PMOS switches to fully turn on the NMOS array, which strengthens the intrinsic NMOS loop and maintains the undershoot and overshoot voltages of 88 and 42 mV, respectively, during an 88.4-mA load transition. In addition, with the aid of the proposed voltage doubler (VD)-based periodically refreshed level shifter (PRLS), the total capacitance of DLDO to drive NMOS array is reduced to 7.2 pF, which is 3.3 \times smaller than that of previous work, extending the input voltage ( V_{\mathrm {IN}} ) and load current ( I_{\mathrm {LOAD}} ) ranges up to 0.9 V and 140 mA, respectively. The proposed DLDO is fabricated using a 28-nm CMOS process and achieves a 0.12-fs speed FoM that is 42.5 \times smaller than the state-of-the-art designs.
AB - A digital low-dropout (DLDO) regulator using p-type MOS (PMOS) and n-type MOS (NMOS) switches is proposed to achieve a sub-fs speed figure-of-merit (FoM) by reducing the total capacitance ( C_{\mathrm {TOT}} ) and accomplishing a comparable output voltage droop ( \Delta V_{\mathrm {OUT}} ) during a load transition. The proposed DLDO uses the segmented PMOS switches to fully turn on the NMOS array, which strengthens the intrinsic NMOS loop and maintains the undershoot and overshoot voltages of 88 and 42 mV, respectively, during an 88.4-mA load transition. In addition, with the aid of the proposed voltage doubler (VD)-based periodically refreshed level shifter (PRLS), the total capacitance of DLDO to drive NMOS array is reduced to 7.2 pF, which is 3.3 \times smaller than that of previous work, extending the input voltage ( V_{\mathrm {IN}} ) and load current ( I_{\mathrm {LOAD}} ) ranges up to 0.9 V and 140 mA, respectively. The proposed DLDO is fabricated using a 28-nm CMOS process and achieves a 0.12-fs speed FoM that is 42.5 \times smaller than the state-of-the-art designs.
KW - Capacitively coupled level shifter (CCLS)
KW - digital low-dropout (DLDO) regulator
KW - fully integrated voltage regulator
KW - periodic charge refresh
KW - power management
UR - http://www.scopus.com/inward/record.url?scp=85085655889&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2019.2952132
DO - 10.1109/JSSC.2019.2952132
M3 - Article
AN - SCOPUS:85085655889
SN - 0018-9200
VL - 55
SP - 1624
EP - 1636
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
M1 - 8905784
ER -