A two-step folder for a high-speed CMOS folding-and-interpolating ADC

Sang Chan Han; Bum Soo Suh; Soo Won Kim

A two-step folder for a high-speed CMOS folding-and-interpolating ADC

Sang Chan Han, Bum Soo Suh, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Optimum design flow of a two-step folder for the input-bandwidth extension of a CMOS folding-and-interpolating ADC is presented. We derived the minimum transistor sizes of the two-step folder and analyzed the effects of the offset voltage. We implemented a folding-and-interpolating ADC adopting the two-step folder in a 0.25 μm 1P-5M CMOS process and got an experimental result of the input bandwidth of 50 MHz. This result verifies the design flow.

Original language	English
Title of host publication	ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages	325-328
Number of pages	4
Publication status	Published - 2001
Event	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta Duration: 2001 Sept 2 → 2001 Sept 5

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	1

Other

Other	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/Territory	Malta
Period	01/9/2 → 01/9/5

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

A two-step folder for a high-speed CMOS folding-and-interpolating ADC. / Han, Sang Chan; Suh, Bum Soo; Kim, Soo Won.
ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. 2001. p. 325-328 957745 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Han, SC, Suh, BS & Kim, SW 2001, A two-step folder for a high-speed CMOS folding-and-interpolating ADC. in ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems., 957745, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 325-328, 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, 01/9/2.

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abstract = "Optimum design flow of a two-step folder for the input-bandwidth extension of a CMOS folding-and-interpolating ADC is presented. We derived the minimum transistor sizes of the two-step folder and analyzed the effects of the offset voltage. We implemented a folding-and-interpolating ADC adopting the two-step folder in a 0.25 μm 1P-5M CMOS process and got an experimental result of the input bandwidth of 50 MHz. This result verifies the design flow.",

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AU - Suh, Bum Soo

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N2 - Optimum design flow of a two-step folder for the input-bandwidth extension of a CMOS folding-and-interpolating ADC is presented. We derived the minimum transistor sizes of the two-step folder and analyzed the effects of the offset voltage. We implemented a folding-and-interpolating ADC adopting the two-step folder in a 0.25 μm 1P-5M CMOS process and got an experimental result of the input bandwidth of 50 MHz. This result verifies the design flow.

AB - Optimum design flow of a two-step folder for the input-bandwidth extension of a CMOS folding-and-interpolating ADC is presented. We derived the minimum transistor sizes of the two-step folder and analyzed the effects of the offset voltage. We implemented a folding-and-interpolating ADC adopting the two-step folder in a 0.25 μm 1P-5M CMOS process and got an experimental result of the input bandwidth of 50 MHz. This result verifies the design flow.

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T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

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BT - ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems

T2 - 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001

Y2 - 2 September 2001 through 5 September 2001

ER -

A two-step folder for a high-speed CMOS folding-and-interpolating ADC

Abstract

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