TY - GEN
T1 - A wide-range all-digital multiphase DLL with supply noise tolerance
AU - Chae, Hyunsoo
AU - Shin, Dongsuk
AU - Kim, Kisoo
AU - Kim, Kwan Weon
AU - Choi, Young Jung
AU - Kim, Chulwoo
PY - 2008
Y1 - 2008
N2 - An 80-to-832MHz all-digital 8-differential-phase DLL in a 0.18um CMOS process has been developed to achieve low-jitter and supply noise tolerance using dual window phase detector, noise tolerant delay cell and delay compensation under supply noise. The proposed DLL occupies 0.19mm2 and dissipates 48mW at 832MHz from a 1.8V supply. The peak-to-peak jitter and rms jitter are 12ps and 1.73ps with a quiet supply at 832MHz, respectively. The peak-to-peak and rms jitter with a 100mV peak-to-peak triangular supply noise at 100MHz are 21ps and 2.99ps, respectively.
AB - An 80-to-832MHz all-digital 8-differential-phase DLL in a 0.18um CMOS process has been developed to achieve low-jitter and supply noise tolerance using dual window phase detector, noise tolerant delay cell and delay compensation under supply noise. The proposed DLL occupies 0.19mm2 and dissipates 48mW at 832MHz from a 1.8V supply. The peak-to-peak jitter and rms jitter are 12ps and 1.73ps with a quiet supply at 832MHz, respectively. The peak-to-peak and rms jitter with a 100mV peak-to-peak triangular supply noise at 100MHz are 21ps and 2.99ps, respectively.
UR - http://www.scopus.com/inward/record.url?scp=67649973970&partnerID=8YFLogxK
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U2 - 10.1109/ASSCC.2008.4708817
DO - 10.1109/ASSCC.2008.4708817
M3 - Conference contribution
AN - SCOPUS:67649973970
SN - 9781424426058
T3 - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
SP - 421
EP - 424
BT - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
T2 - 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Y2 - 3 November 2008 through 5 November 2008
ER -