Abstract
A WR1.5 frequency multiplier circuit using standard CMOS 65nm technology is presented. Careful choice of device and its gate size leads to fair amount of output power compared to other expensive high performance semiconductor process. Accumulation-mode varactor device is chosen for its high non-linearity and gate size of the varactor is enlarged until self-resonance occur at fundamental frequency. Simple doubler circuit is designed using single-balanced topology. Two types of power measurements are performed to verify results. The maximum output power of -21.8dBm is obtained at 59 GHz which is comparable output power considering process cost.
Original language | English |
---|---|
Title of host publication | 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 4666-4669 |
Number of pages | 4 |
ISBN (Electronic) | 9781509060931 |
DOIs | |
Publication status | Published - 2016 Nov 3 |
Event | 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Shanghai, China Duration: 2016 Aug 8 → 2016 Aug 11 |
Publication series
Name | 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings |
---|
Conference
Conference | 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 |
---|---|
Country/Territory | China |
City | Shanghai |
Period | 16/8/8 → 16/8/11 |
Bibliographical note
Funding Information:This work is supported by a grant to Terahertz Electronic Device Research Laboratory funded by Defense Acquisition Program Administration, and by Agency for Defense Development (UD150043RD).
Publisher Copyright:
© 2016 IEEE.
ASJC Scopus subject areas
- Instrumentation
- Radiation
- Electrical and Electronic Engineering
- Atomic and Molecular Physics, and Optics