A WR1.5 frequency multiplier using CMOS accumulation mode varactor device

S. H. Choi; C. Yi; M. Kim

doi:10.1109/PIERS.2016.7735717

A WR1.5 frequency multiplier using CMOS accumulation mode varactor device

S. H. Choi, C. Yi, M. Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A WR1.5 frequency multiplier circuit using standard CMOS 65nm technology is presented. Careful choice of device and its gate size leads to fair amount of output power compared to other expensive high performance semiconductor process. Accumulation-mode varactor device is chosen for its high non-linearity and gate size of the varactor is enlarged until self-resonance occur at fundamental frequency. Simple doubler circuit is designed using single-balanced topology. Two types of power measurements are performed to verify results. The maximum output power of -21.8dBm is obtained at 59 GHz which is comparable output power considering process cost.

Original language	English
Title of host publication	2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	4666-4669
Number of pages	4
ISBN (Electronic)	9781509060931
DOIs	https://doi.org/10.1109/PIERS.2016.7735717
Publication status	Published - 2016 Nov 3
Event	2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Shanghai, China Duration: 2016 Aug 8 → 2016 Aug 11

Publication series

Name	2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings

Conference

Conference	2016 Progress In Electromagnetics Research Symposium, PIERS 2016
Country/Territory	China
City	Shanghai
Period	16/8/8 → 16/8/11

ASJC Scopus subject areas

Instrumentation
Radiation
Electrical and Electronic Engineering
Atomic and Molecular Physics, and Optics

Access to Document

10.1109/PIERS.2016.7735717

Cite this

Choi, S. H., Yi, C., & Kim, M. (2016). A WR1.5 frequency multiplier using CMOS accumulation mode varactor device. In 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings (pp. 4666-4669). Article 7735717 (2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PIERS.2016.7735717

A WR1.5 frequency multiplier using CMOS accumulation mode varactor device. / Choi, S. H.; Yi, C.; Kim, M.
2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. p. 4666-4669 7735717 (2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Choi, SH, Yi, C & Kim, M 2016, A WR1.5 frequency multiplier using CMOS accumulation mode varactor device. in 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings., 7735717, 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 4666-4669, 2016 Progress In Electromagnetics Research Symposium, PIERS 2016, Shanghai, China, 16/8/8. https://doi.org/10.1109/PIERS.2016.7735717

Choi SH, Yi C, Kim M. A WR1.5 frequency multiplier using CMOS accumulation mode varactor device. In 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. p. 4666-4669. 7735717. (2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings). doi: 10.1109/PIERS.2016.7735717

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abstract = "A WR1.5 frequency multiplier circuit using standard CMOS 65nm technology is presented. Careful choice of device and its gate size leads to fair amount of output power compared to other expensive high performance semiconductor process. Accumulation-mode varactor device is chosen for its high non-linearity and gate size of the varactor is enlarged until self-resonance occur at fundamental frequency. Simple doubler circuit is designed using single-balanced topology. Two types of power measurements are performed to verify results. The maximum output power of -21.8dBm is obtained at 59 GHz which is comparable output power considering process cost.",

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A WR1.5 frequency multiplier using CMOS accumulation mode varactor device

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