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A WR1.5 frequency multiplier using CMOS accumulation mode varactor device
S. H. Choi
, C. Yi
,
M. Kim
School of Electrical Engineering
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Chapter in Book/Report/Conference proceeding
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Dive into the research topics of 'A WR1.5 frequency multiplier using CMOS accumulation mode varactor device'. Together they form a unique fingerprint.
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Keyphrases
Power Output
100%
Frequency multiplier
100%
Gate Size
100%
Varactor Device
100%
Accumulation-mode Varactor
100%
High Performance
50%
Standard CMOS Technology
50%
Maximum Output Power
50%
Power Types
50%
Multiplier Circuit
50%
Power Measurement
50%
Semiconductor Process
50%
High Linearity
50%
Varactor
50%
Fundamental Frequency
50%
65nm CMOS
50%
Balanced-to-single-ended
50%
Process Cost
50%
65 Nm Technology
50%
Self-resonance
50%
Balanced Topology
50%
Doubler Circuit
50%
Engineering
Frequency Multiplier
100%
Varactor
100%
Output Power
66%
Maximum Output Power
33%
Fundamental Frequency
33%
Nonlinearity
33%