Access region cache: A multi-porting solution for future wide-issue processors

B. S. Thakar, G. Lee

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)

Abstract

Wide-issue processors issuing tens of instructions per cycle, put heavy stress on the memory system, including data caches. For wide-issue architecture, data cache needs to be heavily multi-ported with extremely wide data-paths. This paper studies a scalable solution to achieve multi-porting with short data-paths and less hardware complexity at higher clock-rates. Our approach divides memory streams into multiple independent sub-streams with the help of prediction mechanism before they enter the reservation stations. Partitioned memory-reference instructions are then fed into separate memory pipelines, each of which is connected to a small data-cache, called access region cache. The separation of independent memory references, in an ideal situation, facilitates the use of multiple caches with smaller number of ports and thus increases the data-bandwidth. We describe and evaluate a wide-issue processor with distinct memory pipelines, driven by a prediction mechanism. The potential performance of the proposed design is measured by comparing it with existing multi-porting solution as well as an ideal multi-ported data cache.

Original languageEnglish
Pages293-300
Number of pages8
Publication statusPublished - 2001
Externally publishedYes
EventIEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001) - Austin, TX, United States
Duration: 2001 Sept 232001 Sept 26

Other

OtherIEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001)
Country/TerritoryUnited States
CityAustin, TX
Period01/9/2301/9/26

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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