Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8% with the selection of four different clock cycles under a supply voltage of 0.3 V.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2012|
Bibliographical noteFunding Information:
Manuscript received January 7, 2012; revised April 17, 2012; accepted June 21, 2012. Date of publication July 23, 2012; date of current version September 11, 2012. This work was supported by the National Research Foundation of Korea Grant 2011-0020128 funded by the Korea Government (Ministry of Education, Science, and Technology). This brief was recommended by Associate Editor Y. Ha.
- Active leakage energy
- subthreshold logics
- ultralow voltage
ASJC Scopus subject areas
- Electrical and Electronic Engineering