Adaptive ECC for Tailored Protection of Nanoscale Memory

Dongyeob Shin, Jongsun Park, Jangwon Park, Somnath Paul, Swarup Bhunia

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


Editors note:Following technology scaling, runtime failure has emerged as one of the major challenges in modern VLSI designs under the increased parametric variability and low supply voltage. This issue is especially severe in nanoscale memory due to its high density and large capacity. In this work the authors present a novel reconfigurable Error Correction Code (ECC) to improve the reliability of nanoscale memory.

Original languageEnglish
Article number7586136
Pages (from-to)84-93
Number of pages10
JournalIEEE Design and Test
Issue number6
Publication statusPublished - 2017 Dec

Bibliographical note

Funding Information:
This work was supported in part by Semiconductor Research Corporation (SRC) under Grant 2650.001, by the National Research Foundation of Korea (#2015M3D1A1070465 and #2016R1A2B4015329), and by the Information Technology Research and Development Program of the Korea Evaluation Institute of Industrial Technology (KEIT) [10052716, Design Technology Development of Ultralow Voltage Operating Circuit and IP for Smart Sensor SoC].

Publisher Copyright:
©2017 IEEE.


  • Error Correction Code (ECC)
  • Memory Failures
  • Robust Nanoscale Memory
  • Run-time Protection
  • Variable ECC

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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