An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier

Yunsoo Park; Jaegeun Song; Yohan Choi; Chaegang Lim; Soonsung Ahn; Chulwoo Kim

doi:10.1109/JSSC.2020.2987684

An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier

Yunsoo Park, Jaegeun Song, Yohan Choi, Chaegang Lim, Soonsung Ahn, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

This article reports a high-linearity dynamic amplifier with a gain control technique for pipelined analog-to-digital converters (ADCs). The wide input range and dynamic operation of the amplifier allow the ADC energy-efficient pipeline process. The voltage gain is controlled in the analog domain with digital gain correction codes, enabling simple compensation for process, voltage, and temperature variations. The proposed switching technique for the amplifier also defines a stable common-mode output without any dedicated hardware. An 11-bit 100-MS/s fully dynamic pipelined ADC using the open-loop dynamic amplifier is implemented without gain-linearity calibration. An ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.05 mm2, and the performances are measured at sampling rates in the range of 10-100 MHz. This ADC achieves a signal-to-noise and distortion ratio of 62 dB and a spurious-free dynamic range of 77 dB while consuming 1.33 mW of power at 100 MS/s. A Walden figure of merit of 10.8-13.1 fJ/conversion-step is achieved.

Original language	English
Article number	9079902
Pages (from-to)	2468-2477
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	55
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2020.2987684
Publication status	Published - 2020 Sept

Bibliographical note

Funding Information:
Manuscript received December 11, 2019; revised February 14, 2020; accepted March 14, 2020. Date of publication April 28, 2020; date of current version August 26, 2020. This article was approved by Associate Editor Piero Malcovati. This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIT) under Grant 2019R1A2B5B03100756. (Corresponding author: Chulwoo Kim.) The authors are with the Department of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: [email protected]).

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

Analog-to-digital conversion
dynamic residue amplifier
fully dynamic pipelined analog-to-digital converter (ADC)
integrator
linearity
open-loop amplifier

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2020.2987684

Cite this

@article{24807db2aa7342e59a5397416a699e5c,

title = "An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier",

abstract = "This article reports a high-linearity dynamic amplifier with a gain control technique for pipelined analog-to-digital converters (ADCs). The wide input range and dynamic operation of the amplifier allow the ADC energy-efficient pipeline process. The voltage gain is controlled in the analog domain with digital gain correction codes, enabling simple compensation for process, voltage, and temperature variations. The proposed switching technique for the amplifier also defines a stable common-mode output without any dedicated hardware. An 11-bit 100-MS/s fully dynamic pipelined ADC using the open-loop dynamic amplifier is implemented without gain-linearity calibration. An ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.05 mm2, and the performances are measured at sampling rates in the range of 10-100 MHz. This ADC achieves a signal-to-noise and distortion ratio of 62 dB and a spurious-free dynamic range of 77 dB while consuming 1.33 mW of power at 100 MS/s. A Walden figure of merit of 10.8-13.1 fJ/conversion-step is achieved.",

keywords = "Analog-to-digital conversion, dynamic residue amplifier, fully dynamic pipelined analog-to-digital converter (ADC), integrator, linearity, open-loop amplifier",

author = "Yunsoo Park and Jaegeun Song and Yohan Choi and Chaegang Lim and Soonsung Ahn and Chulwoo Kim",

note = "Funding Information: Manuscript received December 11, 2019; revised February 14, 2020; accepted March 14, 2020. Date of publication April 28, 2020; date of current version August 26, 2020. This article was approved by Associate Editor Piero Malcovati. This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIT) under Grant 2019R1A2B5B03100756. (Corresponding author: Chulwoo Kim.) The authors are with the Department of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: [email protected]). Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

year = "2020",

month = sep,

doi = "10.1109/JSSC.2020.2987684",

language = "English",

volume = "55",

pages = "2468--2477",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier

AU - Park, Yunsoo

AU - Song, Jaegeun

AU - Choi, Yohan

AU - Lim, Chaegang

AU - Ahn, Soonsung

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received December 11, 2019; revised February 14, 2020; accepted March 14, 2020. Date of publication April 28, 2020; date of current version August 26, 2020. This article was approved by Associate Editor Piero Malcovati. This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIT) under Grant 2019R1A2B5B03100756. (Corresponding author: Chulwoo Kim.) The authors are with the Department of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: [email protected]). Publisher Copyright: © 1966-2012 IEEE.

PY - 2020/9

Y1 - 2020/9

N2 - This article reports a high-linearity dynamic amplifier with a gain control technique for pipelined analog-to-digital converters (ADCs). The wide input range and dynamic operation of the amplifier allow the ADC energy-efficient pipeline process. The voltage gain is controlled in the analog domain with digital gain correction codes, enabling simple compensation for process, voltage, and temperature variations. The proposed switching technique for the amplifier also defines a stable common-mode output without any dedicated hardware. An 11-bit 100-MS/s fully dynamic pipelined ADC using the open-loop dynamic amplifier is implemented without gain-linearity calibration. An ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.05 mm2, and the performances are measured at sampling rates in the range of 10-100 MHz. This ADC achieves a signal-to-noise and distortion ratio of 62 dB and a spurious-free dynamic range of 77 dB while consuming 1.33 mW of power at 100 MS/s. A Walden figure of merit of 10.8-13.1 fJ/conversion-step is achieved.

AB - This article reports a high-linearity dynamic amplifier with a gain control technique for pipelined analog-to-digital converters (ADCs). The wide input range and dynamic operation of the amplifier allow the ADC energy-efficient pipeline process. The voltage gain is controlled in the analog domain with digital gain correction codes, enabling simple compensation for process, voltage, and temperature variations. The proposed switching technique for the amplifier also defines a stable common-mode output without any dedicated hardware. An 11-bit 100-MS/s fully dynamic pipelined ADC using the open-loop dynamic amplifier is implemented without gain-linearity calibration. An ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.05 mm2, and the performances are measured at sampling rates in the range of 10-100 MHz. This ADC achieves a signal-to-noise and distortion ratio of 62 dB and a spurious-free dynamic range of 77 dB while consuming 1.33 mW of power at 100 MS/s. A Walden figure of merit of 10.8-13.1 fJ/conversion-step is achieved.

KW - Analog-to-digital conversion

KW - dynamic residue amplifier

KW - fully dynamic pipelined analog-to-digital converter (ADC)

KW - integrator

KW - linearity

KW - open-loop amplifier

UR - http://www.scopus.com/inward/record.url?scp=85090843022&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2020.2987684

DO - 10.1109/JSSC.2020.2987684

M3 - Article

AN - SCOPUS:85090843022

SN - 0018-9200

VL - 55

SP - 2468

EP - 2477

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 9

M1 - 9079902

ER -

An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this