An 80-dB SNR 4th-order discrete-time sigma-delta modulator

Chan Keun Kwon; Chan Hui Jeong; Young Jae Min; Young Mok Jung; Soo Won Kim

doi:10.1109/ISICir.2011.6131938

An 80-dB SNR 4th-order discrete-time sigma-delta modulator

Chan Keun Kwon, Chan Hui Jeong, Young Jae Min, Young Mok Jung, Soo Won Kim

* Honorary professors

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a 4th-order single-bit DT ΔΣ modulator for audio applications. To achieve higher signal-to-noise ratio (SNR), the compensation capacitors in the input of a comparator are exploited to reduce the metastability of a comparator. The proposed modulator has been fabricated in a quantizer level 0.18-μm CMOS process. Measurements show a SNR of 80.27 dB and a signal-to-noise and distortion ratio (SNDR) of 77.58 dB over a 40-kHz signal bandwidth with a sampling clock frequency of 10.24 MHz. A total power consumption including a clock generator is 340 μW with a 1.8-V supply voltage.

Original language	English
Title of host publication	2011 International Symposium on Integrated Circuits, ISIC 2011
Pages	230-233
Number of pages	4
DOIs	https://doi.org/10.1109/ISICir.2011.6131938
Publication status	Published - 2011
Event	2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore Duration: 2011 Dec 12 → 2011 Dec 14

Publication series

Name	2011 International Symposium on Integrated Circuits, ISIC 2011

Other

Other	2011 International Symposium on Integrated Circuits, ISIC 2011
Country/Territory	Singapore
City	SingaporeSingapore
Period	11/12/12 → 11/12/14

Keywords

Analog-to-digital converter
Comparator-metastability
Compensation capacitor
Discrete-time ΔΣ modulator

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISICir.2011.6131938

Cite this

Kwon, CK, Jeong, CH, Min, YJ, Jung, YM & Kim, SW 2011, An 80-dB SNR 4th-order discrete-time sigma-delta modulator. in 2011 International Symposium on Integrated Circuits, ISIC 2011., 6131938, 2011 International Symposium on Integrated Circuits, ISIC 2011, pp. 230-233, 2011 International Symposium on Integrated Circuits, ISIC 2011, SingaporeSingapore, Singapore, 11/12/12. https://doi.org/10.1109/ISICir.2011.6131938

@inproceedings{32fd29b4f07b4017b008ef728623cc97,

title = "An 80-dB SNR 4th-order discrete-time sigma-delta modulator",

abstract = "This paper presents a 4th-order single-bit DT ΔΣ modulator for audio applications. To achieve higher signal-to-noise ratio (SNR), the compensation capacitors in the input of a comparator are exploited to reduce the metastability of a comparator. The proposed modulator has been fabricated in a quantizer level 0.18-μm CMOS process. Measurements show a SNR of 80.27 dB and a signal-to-noise and distortion ratio (SNDR) of 77.58 dB over a 40-kHz signal bandwidth with a sampling clock frequency of 10.24 MHz. A total power consumption including a clock generator is 340 μW with a 1.8-V supply voltage.",

keywords = "Analog-to-digital converter, Comparator-metastability, Compensation capacitor, Discrete-time ΔΣ modulator",

author = "Kwon, {Chan Keun} and Jeong, {Chan Hui} and Min, {Young Jae} and Jung, {Young Mok} and Kim, {Soo Won}",

year = "2011",

doi = "10.1109/ISICir.2011.6131938",

language = "English",

isbn = "9781612848648",

series = "2011 International Symposium on Integrated Circuits, ISIC 2011",

pages = "230--233",

booktitle = "2011 International Symposium on Integrated Circuits, ISIC 2011",

note = "2011 International Symposium on Integrated Circuits, ISIC 2011 ; Conference date: 12-12-2011 Through 14-12-2011",

}

TY - GEN

T1 - An 80-dB SNR 4th-order discrete-time sigma-delta modulator

AU - Kwon, Chan Keun

AU - Jeong, Chan Hui

AU - Min, Young Jae

AU - Jung, Young Mok

AU - Kim, Soo Won

PY - 2011

Y1 - 2011

N2 - This paper presents a 4th-order single-bit DT ΔΣ modulator for audio applications. To achieve higher signal-to-noise ratio (SNR), the compensation capacitors in the input of a comparator are exploited to reduce the metastability of a comparator. The proposed modulator has been fabricated in a quantizer level 0.18-μm CMOS process. Measurements show a SNR of 80.27 dB and a signal-to-noise and distortion ratio (SNDR) of 77.58 dB over a 40-kHz signal bandwidth with a sampling clock frequency of 10.24 MHz. A total power consumption including a clock generator is 340 μW with a 1.8-V supply voltage.

AB - This paper presents a 4th-order single-bit DT ΔΣ modulator for audio applications. To achieve higher signal-to-noise ratio (SNR), the compensation capacitors in the input of a comparator are exploited to reduce the metastability of a comparator. The proposed modulator has been fabricated in a quantizer level 0.18-μm CMOS process. Measurements show a SNR of 80.27 dB and a signal-to-noise and distortion ratio (SNDR) of 77.58 dB over a 40-kHz signal bandwidth with a sampling clock frequency of 10.24 MHz. A total power consumption including a clock generator is 340 μW with a 1.8-V supply voltage.

KW - Analog-to-digital converter

KW - Comparator-metastability

KW - Compensation capacitor

KW - Discrete-time ΔΣ modulator

UR - http://www.scopus.com/inward/record.url?scp=84863057618&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863057618&partnerID=8YFLogxK

U2 - 10.1109/ISICir.2011.6131938

DO - 10.1109/ISICir.2011.6131938

M3 - Conference contribution

AN - SCOPUS:84863057618

SN - 9781612848648

T3 - 2011 International Symposium on Integrated Circuits, ISIC 2011

SP - 230

EP - 233

BT - 2011 International Symposium on Integrated Circuits, ISIC 2011

T2 - 2011 International Symposium on Integrated Circuits, ISIC 2011

Y2 - 12 December 2011 through 14 December 2011

ER -

An 80-dB SNR 4th-order discrete-time sigma-delta modulator

Abstract

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Keywords

ASJC Scopus subject areas

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