An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion

Jeong Don Ihm; Seung Jun Bae; Kwang Il Park; Ho Young Song; Woo Jin Lee; Hyun Jin Kim; Kyung Ho Kim; Ho Kyung Lee; Min Sang Park; Sam Young Bang; Mi Jin Lee; Gil Shin Moon; Young Wook Jang; Suk Won Hwang; Young Chul Cho; Sang Jun Hwang; Dae Hyun Kim; Ji Hoon Lim; Jae Sung Kim; Su Jin Park; Ok Joo Park; Se Mi Yang; Jin Yong Choi; Young Wook Kim; Hyun Kyu Lee; Sung Hoon Kim; Seong Jin Jang; Young Hyun Jun; Soo In Cho

doi:10.1109/ISSCC.2007.373509

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion

Jeong Don Ihm, Seung Jun Bae, Kwang Il Park, Ho Young Song, Woo Jin Lee, Hyun Jin Kim, Kyung Ho Kim, Ho Kyung Lee, Min Sang Park, Sam Young Bang, Mi Jin Lee, Gil Shin Moon, Young Wook Jang, Suk Won Hwang, Young Chul Cho, Sang Jun Hwang, Dae Hyun Kim, Ji Hoon Lim, Jae Sung Kim, Su Jin ParkOk Joo Park, Se Mi Yang, Jin Yong Choi, Young Wook Kim, Hyun Kyu Lee, Sung Hoon Kim, Seong Jin Jang, Young Hyun Jun, Soo In Cho

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	492-494
Number of pages	3
ISBN (Print)	1424408539, 9781424408535
DOIs	https://doi.org/10.1109/ISSCC.2007.373509
Publication status	Published - 2007
Externally published	Yes
Event	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States Duration: 2007 Feb 11 → 2007 Feb 15

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country/Territory	United States
City	San Francisco, CA
Period	07/2/11 → 07/2/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2007.373509

Cite this

Ihm, J. D., Bae, S. J., Park, K. I., Song, H. Y., Lee, W. J., Kim, H. J., Kim, K. H., Lee, H. K., Park, M. S., Bang, S. Y., Lee, M. J., Moon, G. S., Jang, Y. W., Hwang, S. W., Cho, Y. C., Hwang, S. J., Kim, D. H., Lim, J. H., Kim, J. S., ... Cho, S. I. (2007). An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 492-494). [4242480] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373509

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion. / Ihm, Jeong Don; Bae, Seung Jun; Park, Kwang Il et al.
2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. p. 492-494 4242480 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ihm, JD, Bae, SJ, Park, KI, Song, HY, Lee, WJ, Kim, HJ, Kim, KH, Lee, HK, Park, MS, Bang, SY, Lee, MJ, Moon, GS, Jang, YW, Hwang, SW, Cho, YC, Hwang, SJ, Kim, DH, Lim, JH, Kim, JS, Park, SJ, Park, OJ, Yang, SM, Choi, JY, Kim, YW, Lee, HK, Kim, SH, Jang, SJ, Jun, YH & Cho, SI 2007, An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242480, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 492-494, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373509

Ihm JD, Bae SJ, Park KI, Song HY, Lee WJ, Kim HJ et al. An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. p. 492-494. 4242480. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2007.373509

Ihm, Jeong Don ; Bae, Seung Jun ; Park, Kwang Il et al. / An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion. 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 492-494 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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abstract = "A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.",

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AU - Moon, Gil Shin

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AB - A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.

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An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion

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