TY - GEN
T1 - An all digital time amplifier with interpolation scheme for low gain variation
AU - Dhar, Debashis
AU - Kwak, Young Ho
AU - Jung, Inhwa
AU - Kim, Chulwoo
PY - 2010
Y1 - 2010
N2 - An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.
AB - An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.
KW - All digital time amplifier
KW - Interpolation
UR - https://www.scopus.com/pages/publications/79851471660
UR - https://www.scopus.com/pages/publications/79851471660#tab=citedBy
U2 - 10.1109/SOCDC.2010.5682917
DO - 10.1109/SOCDC.2010.5682917
M3 - Conference contribution
AN - SCOPUS:79851471660
SN - 9781424486335
T3 - 2010 International SoC Design Conference, ISOCC 2010
SP - 276
EP - 278
BT - 2010 International SoC Design Conference, ISOCC 2010
T2 - 2010 International SoC Design Conference, ISOCC 2010
Y2 - 22 November 2010 through 23 November 2010
ER -