An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling

Kyunghoon Chung; Jabeom Koo; Soo Won Kim; Chulwoo Kim

doi:10.1109/ASSCC.2007.4425684

An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling

Kyunghoon Chung, Jabeom Koo, Soo Won Kim, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

This paper describes a new delay-locked loop (DLL) based frequency multiplier which includes a lock controller and a PD to prevent false locking and increase locking range relative to conventional DLLs. By using multiple clock phase of the DLL, the lock controller detects whether the VCDL delay is within a correct locking range or not. A differentially controlled edge combiner for frequency multiplication is also proposed. The anti-harmonic DLL-based frequency multiplier implemented in a 0.18 μm CMOS technology occupies an active area of 0.043 mm² and dissipates 36.7 mW at 1.7GHz output clock. The measured RMS and peak-to-peak jitters for the multiplied output clock at 1.7GHz are 2.64ps and 16.8ps, respectively.

Original language	English
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages	276-279
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425684
Publication status	Published - 2007
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: 2007 Nov 12 → 2007 Nov 14

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/Territory	Korea, Republic of
City	Jeju
Period	07/11/12 → 07/11/14

Keywords

DLL
Frequency multiplication and anti-harmonic

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2007.4425684

Cite this

An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling. / Chung, Kyunghoon; Koo, Jabeom; Kim, Soo Won et al.
2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2007. p. 276-279 4425684 (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chung, K, Koo, J, Kim, SW & Kim, C 2007, An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425684, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp. 276-279, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 07/11/12. https://doi.org/10.1109/ASSCC.2007.4425684

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abstract = "This paper describes a new delay-locked loop (DLL) based frequency multiplier which includes a lock controller and a PD to prevent false locking and increase locking range relative to conventional DLLs. By using multiple clock phase of the DLL, the lock controller detects whether the VCDL delay is within a correct locking range or not. A differentially controlled edge combiner for frequency multiplication is also proposed. The anti-harmonic DLL-based frequency multiplier implemented in a 0.18 μm CMOS technology occupies an active area of 0.043 mm2 and dissipates 36.7 mW at 1.7GHz output clock. The measured RMS and peak-to-peak jitters for the multiplied output clock at 1.7GHz are 2.64ps and 16.8ps, respectively.",

keywords = "DLL, Frequency multiplication and anti-harmonic",

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AB - This paper describes a new delay-locked loop (DLL) based frequency multiplier which includes a lock controller and a PD to prevent false locking and increase locking range relative to conventional DLLs. By using multiple clock phase of the DLL, the lock controller detects whether the VCDL delay is within a correct locking range or not. A differentially controlled edge combiner for frequency multiplication is also proposed. The anti-harmonic DLL-based frequency multiplier implemented in a 0.18 μm CMOS technology occupies an active area of 0.043 mm2 and dissipates 36.7 mW at 1.7GHz output clock. The measured RMS and peak-to-peak jitters for the multiplied output clock at 1.7GHz are 2.64ps and 16.8ps, respectively.

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An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling

Abstract

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Keywords

ASJC Scopus subject areas

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