Abstract
This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-μm CMOS process, occupies an active area of 0.043 mm2, and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.
| Original language | English |
|---|---|
| Article number | 5282518 |
| Pages (from-to) | 1130-1134 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 18 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - 2010 Jul |
Bibliographical note
Funding Information:Manuscript received July 19, 2008; revised January 15, 2009; accepted March 02, 2009. First published October 09, 2009; current version published June 25, 2010. This work was supported by the National Research Foundation of Korea (NRF) under a grant funded by the Korean Government (MEST) (R0A-2007-000-20059-0), and chip fabrication was supported by the IC Design Education Center.
Keywords
- Antiharmonic lock
- delay-locked loop (DLL)
- false lock
- frequency multiplication
- limited locking range
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering