An area and power efficient interpolation scheme using variable current control for 10-bit data drivers in mobile active-matrix LCDs

Hyung Min Lee; Yong Joon Jeon; Sung Woo Lee; Byunghun Lee; Gyu Hyeong Cho

doi:10.1109/TCE.2019.2900512

An area and power efficient interpolation scheme using variable current control for 10-bit data drivers in mobile active-matrix LCDs

Hyung Min Lee, Yong Joon Jeon, Sung Woo Lee, Byunghun Lee, Gyu Hyeong Cho

Research output: Contribution to journal › Article › peer-review

16 Citations (Scopus)

Abstract

This paper presents an area and power efficient interpolation scheme using variable current control (VCC) for 10-bit data drivers in mobile active-matrix LCDs. The VCC interpolation can be embedded in buffer amplifiers as sub-digital-to-analog converters (DACs), reducing the DAC area without requiring additional power and conversion time. Moreover, interpolation errors due to transistor nonlinearity can be compensated through delicate current ratio control, optimizing both accuracy and area efficiency of the high-resolution data driver. The prototype 10-bit data driver with a 6-bit resistor DAC and a 4-bit interpolation sub-DAC occupies the chip area of 460 μm × 14 μm per channel, which is 10.7% smaller than the conventional 8-bit data driver. The data driver consumes static current of 1 μA channel without dissipating additional power for interpolation. The measured integral nonlinearity and differential nonlinearity are 0.4 LSB and 0.7 LSB, respectively. The proposed scheme has competitive performance in terms of driving accuracy, chip size shrinkage, and static power consumption for high-resolution data drivers.

Original language	English
Article number	8648213
Pages (from-to)	253-262
Number of pages	10
Journal	IEEE Transactions on Consumer Electronics
Volume	65
Issue number	2
DOIs	https://doi.org/10.1109/TCE.2019.2900512
Publication status	Published - 2019 May

Bibliographical note

Funding Information:
Manuscript received July 17, 2018; revised December 17, 2018 and January 29, 2019; accepted February 15, 2019. Date of publication February 21, 2019; date of current version April 23, 2019. This work was supported by the System-LSI Division, Samsung Electronics Company, Ltd. (Corresponding author: Byunghun Lee.) H.-M. Lee is with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]). Y.-J. Jeon is with the Institute of Microelectronics, A*STAR, Singapore 138634 (e-mail: [email protected]). S.-W. Lee is with the System-LSI Division, Samsung Electronics, Hwaseong 18448, South Korea (e-mail: [email protected]). B. Lee is with the Department of Electrical Engineering, Incheon National University, Incheon 22012, South Korea (e-mail: [email protected]). G.-H. Cho is with the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 34141, South Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TCE.2019.2900512

Publisher Copyright:
© 1975-2011 IEEE.

Keywords

Buffer amplifier
LCD
data driver
digital-to-analog converter (DAC)
interpolation
piecewise linear
variable current control (VCC)

ASJC Scopus subject areas

Media Technology
Electrical and Electronic Engineering

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10.1109/TCE.2019.2900512

Cite this

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title = "An area and power efficient interpolation scheme using variable current control for 10-bit data drivers in mobile active-matrix LCDs",

abstract = "This paper presents an area and power efficient interpolation scheme using variable current control (VCC) for 10-bit data drivers in mobile active-matrix LCDs. The VCC interpolation can be embedded in buffer amplifiers as sub-digital-to-analog converters (DACs), reducing the DAC area without requiring additional power and conversion time. Moreover, interpolation errors due to transistor nonlinearity can be compensated through delicate current ratio control, optimizing both accuracy and area efficiency of the high-resolution data driver. The prototype 10-bit data driver with a 6-bit resistor DAC and a 4-bit interpolation sub-DAC occupies the chip area of 460 μm × 14 μm per channel, which is 10.7% smaller than the conventional 8-bit data driver. The data driver consumes static current of 1 μA channel without dissipating additional power for interpolation. The measured integral nonlinearity and differential nonlinearity are 0.4 LSB and 0.7 LSB, respectively. The proposed scheme has competitive performance in terms of driving accuracy, chip size shrinkage, and static power consumption for high-resolution data drivers.",

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author = "Lee, {Hyung Min} and Jeon, {Yong Joon} and Lee, {Sung Woo} and Byunghun Lee and Cho, {Gyu Hyeong}",

note = "Funding Information: Manuscript received July 17, 2018; revised December 17, 2018 and January 29, 2019; accepted February 15, 2019. Date of publication February 21, 2019; date of current version April 23, 2019. This work was supported by the System-LSI Division, Samsung Electronics Company, Ltd. (Corresponding author: Byunghun Lee.) H.-M. Lee is with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]). Y.-J. Jeon is with the Institute of Microelectronics, A*STAR, Singapore 138634 (e-mail: [email protected]). S.-W. Lee is with the System-LSI Division, Samsung Electronics, Hwaseong 18448, South Korea (e-mail: [email protected]). B. Lee is with the Department of Electrical Engineering, Incheon National University, Incheon 22012, South Korea (e-mail: [email protected]). G.-H. Cho is with the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 34141, South Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TCE.2019.2900512 Publisher Copyright: {\textcopyright} 1975-2011 IEEE.",

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An area and power efficient interpolation scheme using variable current control for 10-bit data drivers in mobile active-matrix LCDs

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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