An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme with the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications

The timing skew between signals reduces the timing margin of the receiver and limits the data rate of the parallel link. This issue becomes more critical for applications with many IO pins, such as a high bandwidth memory (HBM). The inter-signal skew compensation scheme for many IO pins requires not only de-skew performance but also the minimization of area and power overheads. In this brief, we propose an inter-pin skew compensation scheme using bypass-controlled all digital delay locked loops (ADDLL). The adoption of the proposed bypass control register that operates with a binary search algorithm, such as the successive approximation register (SAR), allows the digital control delay line (DCDL) controller to be embedded in the delay line. This can alleviate the limitation of bandwidth, which is a disadvantage of SAR and occupies smaller area than SAR whereas maintaining the fast lock time. The circuit is fabricated using a 28 nm CMOS technology with a 1 V supply voltage and an area of 0.0009 mm2 for one de-skew module. The measured result shows that inter-signal skew is reduced to less than 3 ps for 2 Gb/s/pin $\times8$ parallel signals.