An efficient off-chip impedance matching technique of L-band silicon integrated circuits

An efficient off-chip impedance matching technique of RF silicon IC's is presented. SPICE simulation of the chip including the package components such as lead frames, bonding wires, and pads is shown to be adequate enough for the construction of the matching networks and the S-parameter measurements of the inputs are not needed. Experimental results show that satisfactory off-chip impedance matching has been achieved using this technique. Simulation result of IF signal well describes measured time domain, and the measured input reflection coefficient (S ₁₁) is shown to reach near the -25 dB point.