An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Joonho Kong, Farinaz Koushanfar, Sung Woo Chung

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)


As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., die-stacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3D microprocessors. In this paper, we propose a novel cache architecture that exploits narrow-width values for yield improvement of LLCs (in this paper, L2 caches) in 3D microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy-efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.

Original languageEnglish
Article number6977972
Pages (from-to)2460-2475
Number of pages16
JournalIEEE Transactions on Computers
Issue number9
Publication statusPublished - 2015 Sept 1

Bibliographical note

Publisher Copyright:
© 1968-2012 IEEE.


  • 3D microprocessor
  • Last-level cache
  • Leakage energy optimization
  • Narrow-width value
  • Process variation
  • Yield

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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