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An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors
Joonho Kong
*
, Farinaz Koushanfar
,
Sung Woo Chung
*
Corresponding author for this work
Research output
:
Contribution to journal
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Article
›
peer-review
8
Citations (Scopus)
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Dive into the research topics of 'An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors'. Together they form a unique fingerprint.
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Keyphrases
Energy Efficient
100%
Last-level Cache
100%
Process Variation
100%
Variation Tolerance
100%
Cache Architecture
100%
3D Microprocessor
100%
Caching
75%
Yield Loss
75%
Proposed Architecture
50%
L2 Cache
50%
Microprocessor
25%
SRAM Cell
25%
Energy Performance
25%
Performance Reliability
25%
High Energy Efficiency
25%
Process Technology
25%
Vulnerable Components
25%
Variation Problem
25%
Yield Improvement
25%
Most Vulnerable
25%
Narrow-width Value
25%
Cell Failure
25%
L3 Cache
25%
Computer Science
Energy Efficient
100%
Process Variation
100%
Microprocessor Chips
100%
Energy Efficiency
20%
Energy Performance
20%
Affect Performance
20%
L2 Cache
20%