An Energy-Quality Scalable STDP Based Sparse Coding Processor with On-Chip Learning Capability

Heetak Kim, Hoyoung Tang, Woong Choi, Jongsun Park

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)


Two main bottlenecks encountered when implementing energy-efficient spike-timing-dependent plasticity (STDP) based sparse coding, are the complex computation of winner-take-all (WTA) operation and repetitive neuronal operations in the time domain processing. In this article, we present an energy-efficient STDP based sparse coding processor. The low-cost hardware is based on the algorithmic reduction techniques as following: First, the complex WTA operation is simplified based on the prediction of spike emitting neurons. Sparsity based approximation in spatial and temporal domain are also efficiently exploited to remove the redundant neurons with negligible algorithmic accuracy loss. We designed and implemented the hardware of the STDP based sparse coding using 65nm CMOS process. By exploiting input sparsity, the proposed SNN architecture can dynamically trade off algorithmic quality for computation energy (up to 74%) for Natural image (maximum 0.01 RMSE increment) and MNIST (no accuracy loss) applications. In the inference mode of operations, the SNN hardware achieves the throughput of 374 Mpixels/s and 840.2 GSOP/s with the energy-efficiency of 781.52 pJ/pixel and 0.35 pJ/SOP.

Original languageEnglish
Article number8949731
Pages (from-to)125-137
Number of pages13
JournalIEEE Transactions on Biomedical Circuits and Systems
Issue number1
Publication statusPublished - 2020 Feb 1
Externally publishedYes

Bibliographical note

Funding Information:
Manuscript received July 3, 2019; revised October 12, 2019 and November 27, 2019; accepted December 16, 2019. Date of publication January 3, 2020; date of current version February 4, 2020. This work was supported by the MSIT (Ministry of Science and ICT), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2019-2018-0-01433) supervised by the IITP (Institute for Information & communications Technology Promotion) and the National Research Foundation of Korea (NRF) grant funded by the Korea government (NRF-2015 M3D1A1070465) and the Industrial Strategic Technology Development Program(10077445, Development of SoC technology based on Spiking Neural Cell for smart mobile and IoT Devices) funded By the Ministry of Trade, Industry & Energy(MOTIE, Korea). (Corresponding author: Jongsun Park.) H. Kim is with the SoC Platform Research Center, Korea Electronics Technology Institute (KETI), Seongnam, Gyeonggi-do 13509, Korea (e-mail: htkim@ket

Publisher Copyright:
© 2007-2012 IEEE.


  • Neuromorphic system
  • on-chip learning
  • sparse coding
  • spike timing dependent plasticity (STDP)
  • spiking neural network

ASJC Scopus subject areas

  • Biomedical Engineering
  • Electrical and Electronic Engineering


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