Abstract
This letter presents a modified low-complexity chase (LCC) algorithm, where a fewer number of vectors can be tested with minor error correction performance degradation. The proposed LCC decoding pre-determines whether the number of errors in the received codeword is even or odd, and it processes only necessary test vectors. As a result, the number of test vectors can be reduced by half compared to the conventional LCC decoding. The Reed-Solomon (255,239) decoder with the proposed LCC algorithm has been implemented using 65nm CMOS process. The hardware implementation results show that the proposed decoder shows 48.5% reduced latency with 0.06 dB of coding gain decrease at $\mathbf {10^{-6}}$ codeword error rate compared to the state-of-the-art LCC decoder.
Original language | English |
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Article number | 9336031 |
Pages (from-to) | 1505-1509 |
Number of pages | 5 |
Journal | IEEE Communications Letters |
Volume | 25 |
Issue number | 5 |
DOIs | |
Publication status | Published - 2021 May |
Bibliographical note
Publisher Copyright:© 1997-2012 IEEE.
Keywords
- Reed-Solomon (RS) codes
- algebraic soft-decision decoding (ASD)
- latency
- low-complexity chase (LCC)
ASJC Scopus subject areas
- Modelling and Simulation
- Computer Science Applications
- Electrical and Electronic Engineering