An inverter layout technique for propagation delay minimization

Ji Hak Yu; Chan Keun Kwon; Junil Moon; Soo-Won Kim

doi:10.1109/ISCE.2015.7177790

An inverter layout technique for propagation delay minimization

Ji Hak Yu, Chan Keun Kwon, Junil Moon, Soo-Won Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.

Original language	English
Title of host publication	2015 International Symposium on Consumer Electronics, ISCE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Volume	2015-August
ISBN (Electronic)	9781467373654
DOIs	https://doi.org/10.1109/ISCE.2015.7177790
Publication status	Published - 2015 Aug 4
Event	IEEE International Symposium on Consumer Electronics, ISCE 2015 - Madrid, Spain Duration: 2015 Jun 24 → 2015 Jun 26

Other

Other	IEEE International Symposium on Consumer Electronics, ISCE 2015
Country/Territory	Spain
City	Madrid
Period	15/6/24 → 15/6/26

Keywords

inverter
layout
Propagation delay
Ring oscillator

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/ISCE.2015.7177790

Cite this

Yu, JH, Kwon, CK, Moon, J & Kim, S-W 2015, An inverter layout technique for propagation delay minimization. in 2015 International Symposium on Consumer Electronics, ISCE 2015. vol. 2015-August, 7177790, Institute of Electrical and Electronics Engineers Inc., IEEE International Symposium on Consumer Electronics, ISCE 2015, Madrid, Spain, 15/6/24. https://doi.org/10.1109/ISCE.2015.7177790

@inproceedings{44d07f305070429ca15608d333931be5,

title = "An inverter layout technique for propagation delay minimization",

abstract = "Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.",

keywords = "inverter, layout, Propagation delay, Ring oscillator",

author = "Yu, {Ji Hak} and Kwon, {Chan Keun} and Junil Moon and Soo-Won Kim",

year = "2015",

month = aug,

day = "4",

doi = "10.1109/ISCE.2015.7177790",

language = "English",

volume = "2015-August",

booktitle = "2015 International Symposium on Consumer Electronics, ISCE 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Symposium on Consumer Electronics, ISCE 2015 ; Conference date: 24-06-2015 Through 26-06-2015",

}

TY - GEN

T1 - An inverter layout technique for propagation delay minimization

AU - Yu, Ji Hak

AU - Kwon, Chan Keun

AU - Moon, Junil

AU - Kim, Soo-Won

PY - 2015/8/4

Y1 - 2015/8/4

N2 - Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.

AB - Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.

KW - inverter

KW - layout

KW - Propagation delay

KW - Ring oscillator

UR - http://www.scopus.com/inward/record.url?scp=84953255818&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84953255818&partnerID=8YFLogxK

U2 - 10.1109/ISCE.2015.7177790

DO - 10.1109/ISCE.2015.7177790

M3 - Conference contribution

AN - SCOPUS:84953255818

VL - 2015-August

BT - 2015 International Symposium on Consumer Electronics, ISCE 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Consumer Electronics, ISCE 2015

Y2 - 24 June 2015 through 26 June 2015

ER -

An inverter layout technique for propagation delay minimization

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