An on-chip network fabric supporting coarse-grained processor array

Phi Hung Pham, Phuong Mau, Jungmoon Kim, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)


Coarse grained arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design on-chip communication networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This paper presents a silicon-proven design of a 64-PE circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. A proof-of-concept test chip fabricated in a 0.13 μm CMOS process occupies a silicon area of 23 mm2 and consumes a peak power of 200 mW @ 128 MHz and 1.2 Vcc, at room temperature. The OCN overhead consumes 9.4% of the area and 18% of the power of the total chip. Experimental results and analysis show that the proposed OCN fabric with its dynamic path-setup is suitable for use in an embedded CGA supporting fast run-time reconfigurability.

Original languageEnglish
Article number6142140
Pages (from-to)178-182
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number1
Publication statusPublished - 2013


  • Coarse grained array (CGA)
  • network-on-chip (NoC)
  • on-chip communication network
  • reconfigurable computing

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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