Abstract
This paper presents a new energy-efficient ring oscillator collapse-based comparator, which is demonstrated in a 15-bit SAR ADC. The comparator automatically adjusts comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. The employed SAR ADC supplements a 10-bit differential main CDAC with a 5-bit common-mode CDAC. This offers an additional 5 bits of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40nm CMOS shows 74.12 dB SNDR and 173.4 dB FOMs. The comparator consumes 104 nW with the full ADC consuming 1.17 μW.
Original language | English |
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Title of host publication | 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781509006342 |
DOIs | |
Publication status | Published - 2016 Sept 21 |
Event | 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: 2016 Jun 14 → 2016 Jun 17 |
Publication series
Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
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Volume | 2016-September |
Other
Other | 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 |
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Country/Territory | United States |
City | Honolulu |
Period | 16/6/14 → 16/6/17 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials