Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.
|Title of host publication
|2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 2017 Sept 27
|60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States
Duration: 2017 Aug 6 → 2017 Aug 9
|Midwest Symposium on Circuits and Systems
|60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
|17/8/6 → 17/8/9
Bibliographical notePublisher Copyright:
© 2017 IEEE.
- Deep neural network
- Machine learning accelerator
- Resistive memory
- Resistive processing unit
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering