Abstract
Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.
Original language | English |
---|---|
Title of host publication | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 422-425 |
Number of pages | 4 |
ISBN (Electronic) | 9781509063895 |
DOIs | |
Publication status | Published - 2017 Sept 27 |
Event | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States Duration: 2017 Aug 6 → 2017 Aug 9 |
Publication series
Name | Midwest Symposium on Circuits and Systems |
---|---|
Volume | 2017-August |
ISSN (Print) | 1548-3746 |
Conference
Conference | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
---|---|
Country/Territory | United States |
City | Boston |
Period | 17/8/6 → 17/8/9 |
Bibliographical note
Publisher Copyright:© 2017 IEEE.
Keywords
- Deep neural network
- Machine learning accelerator
- RPU
- Resistive memory
- Resistive processing unit
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering