Analog CMOS-based resistive processing unit for deep neural network training

Seyoung Kim; Tayfun Gokmen; Hyung Min Lee; Wilfried E. Haensch

doi:10.1109/MWSCAS.2017.8052950

Analog CMOS-based resistive processing unit for deep neural network training

Seyoung Kim, Tayfun Gokmen, Hyung Min Lee, Wilfried E. Haensch

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

33 Citations (Scopus)

Abstract

Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.

Original language	English
Title of host publication	2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	422-425
Number of pages	4
ISBN (Electronic)	9781509063895
DOIs	https://doi.org/10.1109/MWSCAS.2017.8052950
Publication status	Published - 2017 Sept 27
Event	60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States Duration: 2017 Aug 6 → 2017 Aug 9

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2017-August
ISSN (Print)	1548-3746

Conference

Conference	60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
Country/Territory	United States
City	Boston
Period	17/8/6 → 17/8/9

Keywords

Deep neural network
Machine learning accelerator
RPU
Resistive memory
Resistive processing unit

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2017.8052950

Cite this

Kim, S., Gokmen, T., Lee, H. M., & Haensch, W. E. (2017). Analog CMOS-based resistive processing unit for deep neural network training. In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017 (pp. 422-425). [8052950] (Midwest Symposium on Circuits and Systems; Vol. 2017-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2017.8052950

Analog CMOS-based resistive processing unit for deep neural network training. / Kim, Seyoung; Gokmen, Tayfun; Lee, Hyung Min et al.
2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 422-425 8052950 (Midwest Symposium on Circuits and Systems; Vol. 2017-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, S, Gokmen, T, Lee, HM & Haensch, WE 2017, Analog CMOS-based resistive processing unit for deep neural network training. in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017., 8052950, Midwest Symposium on Circuits and Systems, vol. 2017-August, Institute of Electrical and Electronics Engineers Inc., pp. 422-425, 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, United States, 17/8/6. https://doi.org/10.1109/MWSCAS.2017.8052950

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abstract = "Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.",

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Analog CMOS-based resistive processing unit for deep neural network training

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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