TY - GEN
T1 - Analog CMOS-based resistive processing unit for deep neural network training
AU - Kim, Seyoung
AU - Gokmen, Tayfun
AU - Lee, Hyung Min
AU - Haensch, Wilfried E.
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/27
Y1 - 2017/9/27
N2 - Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.
AB - Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.
KW - Deep neural network
KW - Machine learning accelerator
KW - RPU
KW - Resistive memory
KW - Resistive processing unit
UR - http://www.scopus.com/inward/record.url?scp=85034014587&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2017.8052950
DO - 10.1109/MWSCAS.2017.8052950
M3 - Conference contribution
AN - SCOPUS:85034014587
T3 - Midwest Symposium on Circuits and Systems
SP - 422
EP - 425
BT - 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
Y2 - 6 August 2017 through 9 August 2017
ER -