Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip

P. T. Hong; Phi Hung Pham; Xuan Tu Tran; Chulwoo Kim

doi:10.1109/cce.2008.4578925

Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip

P. T. Hong, Phi Hung Pham, Xuan Tu Tran, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characterization of on-chip traffics and traffic-performance evaluation are necessary steps bringing comprehensive and effective NoC design. This paper presents an analysis and performance evaluation framework of backtracked routing Network-on-Chip that provides guaranteed and energy-efficient data transfer. Experimental results, under common and application-oriented synthetic traffics, figure out the performance in terms of latency and throughput and suggest a tradeoff to developers to map applications into a proposed NoC platform.

Original language	English
Title of host publication	HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics
Publisher	IEEE Computer Society
Pages	13-17
Number of pages	5
ISBN (Print)	9781424424269
DOIs	https://doi.org/10.1109/cce.2008.4578925
Publication status	Published - 2008
Event	HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics - Hoi an, Viet Nam Duration: 2008 Jun 4 → 2008 Jun 6

Publication series

Name	HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics

Other

Other	HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics
Country/Territory	Viet Nam
City	Hoi an
Period	08/6/4 → 08/6/6

Keywords

Network architecture
Network-on-chip
On-chip communication
On-chip traffics
Performance evaluation

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering
Communication

Access to Document

10.1109/cce.2008.4578925

Cite this

Hong, P. T., Pham, P. H., Tran, X. T., & Kim, C. (2008). Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip. In HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics (pp. 13-17). Article 4578925 (HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics). IEEE Computer Society. https://doi.org/10.1109/cce.2008.4578925

Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip. / Hong, P. T.; Pham, Phi Hung; Tran, Xuan Tu et al.
HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics. IEEE Computer Society, 2008. p. 13-17 4578925 (HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hong, PT, Pham, PH, Tran, XT & Kim, C 2008, Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip. in HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics., 4578925, HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics, IEEE Computer Society, pp. 13-17, HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics, Hoi an, Viet Nam, 08/6/4. https://doi.org/10.1109/cce.2008.4578925

@inproceedings{1fa2ad5b094140ec9753818cd95379be,

title = "Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip",

abstract = "VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characterization of on-chip traffics and traffic-performance evaluation are necessary steps bringing comprehensive and effective NoC design. This paper presents an analysis and performance evaluation framework of backtracked routing Network-on-Chip that provides guaranteed and energy-efficient data transfer. Experimental results, under common and application-oriented synthetic traffics, figure out the performance in terms of latency and throughput and suggest a tradeoff to developers to map applications into a proposed NoC platform.",

keywords = "Network architecture, Network-on-chip, On-chip communication, On-chip traffics, Performance evaluation",

author = "Hong, {P. T.} and Pham, {Phi Hung} and Tran, {Xuan Tu} and Chulwoo Kim",

year = "2008",

doi = "10.1109/cce.2008.4578925",

language = "English",

isbn = "9781424424269",

series = "HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics",

publisher = "IEEE Computer Society",

pages = "13--17",

booktitle = "HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics",

note = "HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics ; Conference date: 04-06-2008 Through 06-06-2008",

}

TY - GEN

T1 - Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip

AU - Hong, P. T.

AU - Pham, Phi Hung

AU - Tran, Xuan Tu

AU - Kim, Chulwoo

PY - 2008

Y1 - 2008

N2 - VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characterization of on-chip traffics and traffic-performance evaluation are necessary steps bringing comprehensive and effective NoC design. This paper presents an analysis and performance evaluation framework of backtracked routing Network-on-Chip that provides guaranteed and energy-efficient data transfer. Experimental results, under common and application-oriented synthetic traffics, figure out the performance in terms of latency and throughput and suggest a tradeoff to developers to map applications into a proposed NoC platform.

AB - VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characterization of on-chip traffics and traffic-performance evaluation are necessary steps bringing comprehensive and effective NoC design. This paper presents an analysis and performance evaluation framework of backtracked routing Network-on-Chip that provides guaranteed and energy-efficient data transfer. Experimental results, under common and application-oriented synthetic traffics, figure out the performance in terms of latency and throughput and suggest a tradeoff to developers to map applications into a proposed NoC platform.

KW - Network architecture

KW - Network-on-chip

KW - On-chip communication

KW - On-chip traffics

KW - Performance evaluation

UR - http://www.scopus.com/inward/record.url?scp=51549091823&partnerID=8YFLogxK

U2 - 10.1109/cce.2008.4578925

DO - 10.1109/cce.2008.4578925

M3 - Conference contribution

AN - SCOPUS:51549091823

SN - 9781424424269

T3 - HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics

SP - 13

EP - 17

BT - HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics

PB - IEEE Computer Society

T2 - HUT-ICCE 2008 - 2nd International Conference on Communications and Electronics

Y2 - 4 June 2008 through 6 June 2008

ER -

Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this