We present a technique for thinning the channel region of silicon nanowires (SiNWs) selectively while maintaining a thickness of the source/drain (S/D) regions in an attempt to minimize the parasitic series resistance of SiNW transistors (SNWTs). By transferring the as-fabricated SiNWs onto a plastic substrate, p-SNWTs were fabricated on a plastic substrate, and carrier transport in p-SNWTs was investigated by extracting electrical parameters using the YΦ method, which include mobility attenuation factors, parasitic series resistance (R sd), and effective channel resistance. It is shown that, in the strong inversion region, the parameters fit the measurement data well and that degradation in device performance in our p-SNWTs under high transverse electric fields is dominated by surface roughness scattering, with minimal R sd impact on it due to the relatively thick S/D regions.
Bibliographical noteFunding Information:
This work was supported by the Future-based Technology Development Program (Nano Fields) through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0019197), World Class University (WCU, R32-2008-000-10082-0), and KSSRC program (Development of printable integrated circuits based on inorganic semiconductor nanowires).
ASJC Scopus subject areas
- Physics and Astronomy (miscellaneous)