Analysis of electrical parameters of p-channel silicon nanowire transistors with selectively thinned channels on plastics

We present a technique for thinning the channel region of silicon nanowires (SiNWs) selectively while maintaining a thickness of the source/drain (S/D) regions in an attempt to minimize the parasitic series resistance of SiNW transistors (SNWTs). By transferring the as-fabricated SiNWs onto a plastic substrate, p-SNWTs were fabricated on a plastic substrate, and carrier transport in p-SNWTs was investigated by extracting electrical parameters using the YΦ method, which include mobility attenuation factors, parasitic series resistance (R _sd), and effective channel resistance. It is shown that, in the strong inversion region, the parameters fit the measurement data well and that degradation in device performance in our p-SNWTs under high transverse electric fields is dominated by surface roughness scattering, with minimal R _sd impact on it due to the relatively thick S/D regions.