Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer

Jin Soo Park; Jung Yeon Kim; Ji Hoon Lee; Hee Kyoung Bae; Jinsik Kim; Kyo Seon Hwang; Jung Ho Park; Rino Choi; Byung Chul Lee

doi:10.1109/ULTSYM.2017.8092012

Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer

Jin Soo Park, Jung Yeon Kim, Ji Hoon Lee, Hee Kyoung Bae, Jinsik Kim, Kyo Seon Hwang, Jung Ho Park, Rino Choi, Byung Chul Lee

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, we present a full analytical model that can simulate an entire CMUT-FET structure with high accuracy and fast computation. Using the proposed analytical model, electromechanical properties, electrical characteristics (I_d-V_g), and pressure sensitivity of the CMUT-FET are simulated and analyzed. The optimal bias point of the CMUT-FET is found to be 1.3 V (Sub-threshold operation), at which the calculated pressure sensitivity is 2.584 × 10^-6 Pa^-1. This optimum bias point is almost 11 times lower than 80 % pull-in voltage for conventional high-frequency CMUTs. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel-silicided source/drain junctions and low-temperature wafer bonding. The low-temperature wafer bonding successfully demonstrates the direct integration of CMUT on FET, which is verified via cross-sectional inspection. The fabrication technique is a promising solution and can be developed further to for integration with ICs.

Original language	English
Title of host publication	2017 IEEE International Ultrasonics Symposium, IUS 2017
Publisher	IEEE Computer Society
ISBN (Electronic)	9781538633830
DOIs	https://doi.org/10.1109/ULTSYM.2017.8092012
Publication status	Published - 2017 Oct 31
Event	2017 IEEE International Ultrasonics Symposium, IUS 2017 - Washington, United States Duration: 2017 Sept 6 → 2017 Sept 9

Publication series

Name	IEEE International Ultrasonics Symposium, IUS
ISSN (Print)	1948-5719
ISSN (Electronic)	1948-5727

Other

Other	2017 IEEE International Ultrasonics Symposium, IUS 2017
Country/Territory	United States
City	Washington
Period	17/9/6 → 17/9/9

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported by the KIST institutional program (2E26180) and Nano͎ Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2015M3A7B7045470). The FET part and low temperature wafer bonding processes were done at Korea National Nanofab Center (NNFC, Daejeon, South Korea) and other post fabrication processes were executed at KIST Micro-Nano Fabrication Center (Seoul, South Korea).

Publisher Copyright:
© 2017 IEEE.

Keywords

Analytical model
Field-effect transistor-embedded capacitive micromachined ultrasonic transducer (CMUT-FET)
High-frequency operation
Low-temperature wafer bonding

ASJC Scopus subject areas

Acoustics and Ultrasonics

Access to Document

10.1109/ULTSYM.2017.8092012

Cite this

Park, J. S., Kim, J. Y., Lee, J. H., Bae, H. K., Kim, J., Hwang, K. S., Park, J. H., Choi, R., & Lee, B. C. (2017). Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer. In 2017 IEEE International Ultrasonics Symposium, IUS 2017 Article 8092012 (IEEE International Ultrasonics Symposium, IUS). IEEE Computer Society. https://doi.org/10.1109/ULTSYM.2017.8092012

Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer. / Park, Jin Soo; Kim, Jung Yeon; Lee, Ji Hoon et al.
2017 IEEE International Ultrasonics Symposium, IUS 2017. IEEE Computer Society, 2017. 8092012 (IEEE International Ultrasonics Symposium, IUS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, JS, Kim, JY, Lee, JH, Bae, HK, Kim, J, Hwang, KS, Park, JH, Choi, R & Lee, BC 2017, Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer. in 2017 IEEE International Ultrasonics Symposium, IUS 2017., 8092012, IEEE International Ultrasonics Symposium, IUS, IEEE Computer Society, 2017 IEEE International Ultrasonics Symposium, IUS 2017, Washington, United States, 17/9/6. https://doi.org/10.1109/ULTSYM.2017.8092012

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title = "Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer",

abstract = "In this paper, we present a full analytical model that can simulate an entire CMUT-FET structure with high accuracy and fast computation. Using the proposed analytical model, electromechanical properties, electrical characteristics (Id-Vg), and pressure sensitivity of the CMUT-FET are simulated and analyzed. The optimal bias point of the CMUT-FET is found to be 1.3 V (Sub-threshold operation), at which the calculated pressure sensitivity is 2.584 × 10-6 Pa-1. This optimum bias point is almost 11 times lower than 80 % pull-in voltage for conventional high-frequency CMUTs. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel-silicided source/drain junctions and low-temperature wafer bonding. The low-temperature wafer bonding successfully demonstrates the direct integration of CMUT on FET, which is verified via cross-sectional inspection. The fabrication technique is a promising solution and can be developed further to for integration with ICs.",

keywords = "Analytical model, Field-effect transistor-embedded capacitive micromachined ultrasonic transducer (CMUT-FET), High-frequency operation, Low-temperature wafer bonding",

author = "Park, {Jin Soo} and Kim, {Jung Yeon} and Lee, {Ji Hoon} and Bae, {Hee Kyoung} and Jinsik Kim and Hwang, {Kyo Seon} and Park, {Jung Ho} and Rino Choi and Lee, {Byung Chul}",

note = "Funding Information: ACKNOWLEDGMENT This work was supported by the KIST institutional program (2E26180) and Nano͎ Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2015M3A7B7045470). The FET part and low temperature wafer bonding processes were done at Korea National Nanofab Center (NNFC, Daejeon, South Korea) and other post fabrication processes were executed at KIST Micro-Nano Fabrication Center (Seoul, South Korea). Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE International Ultrasonics Symposium, IUS 2017 ; Conference date: 06-09-2017 Through 09-09-2017",

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AU - Park, Jin Soo

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AU - Hwang, Kyo Seon

AU - Park, Jung Ho

AU - Choi, Rino

AU - Lee, Byung Chul

N1 - Funding Information: ACKNOWLEDGMENT This work was supported by the KIST institutional program (2E26180) and Nano͎ Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2015M3A7B7045470). The FET part and low temperature wafer bonding processes were done at Korea National Nanofab Center (NNFC, Daejeon, South Korea) and other post fabrication processes were executed at KIST Micro-Nano Fabrication Center (Seoul, South Korea). Publisher Copyright: © 2017 IEEE.

PY - 2017/10/31

Y1 - 2017/10/31

N2 - In this paper, we present a full analytical model that can simulate an entire CMUT-FET structure with high accuracy and fast computation. Using the proposed analytical model, electromechanical properties, electrical characteristics (Id-Vg), and pressure sensitivity of the CMUT-FET are simulated and analyzed. The optimal bias point of the CMUT-FET is found to be 1.3 V (Sub-threshold operation), at which the calculated pressure sensitivity is 2.584 × 10-6 Pa-1. This optimum bias point is almost 11 times lower than 80 % pull-in voltage for conventional high-frequency CMUTs. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel-silicided source/drain junctions and low-temperature wafer bonding. The low-temperature wafer bonding successfully demonstrates the direct integration of CMUT on FET, which is verified via cross-sectional inspection. The fabrication technique is a promising solution and can be developed further to for integration with ICs.

AB - In this paper, we present a full analytical model that can simulate an entire CMUT-FET structure with high accuracy and fast computation. Using the proposed analytical model, electromechanical properties, electrical characteristics (Id-Vg), and pressure sensitivity of the CMUT-FET are simulated and analyzed. The optimal bias point of the CMUT-FET is found to be 1.3 V (Sub-threshold operation), at which the calculated pressure sensitivity is 2.584 × 10-6 Pa-1. This optimum bias point is almost 11 times lower than 80 % pull-in voltage for conventional high-frequency CMUTs. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel-silicided source/drain junctions and low-temperature wafer bonding. The low-temperature wafer bonding successfully demonstrates the direct integration of CMUT on FET, which is verified via cross-sectional inspection. The fabrication technique is a promising solution and can be developed further to for integration with ICs.

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Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer

Abstract

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Bibliographical note

Keywords

ASJC Scopus subject areas

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