TY - GEN
T1 - Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer
AU - Park, Jin Soo
AU - Kim, Jung Yeon
AU - Lee, Ji Hoon
AU - Bae, Hee Kyoung
AU - Kim, Jinsik
AU - Hwang, Kyo Seon
AU - Park, Jung Ho
AU - Choi, Rino
AU - Lee, Byung Chul
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by the KIST institutional program (2E26180) and Nano͎ Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2015M3A7B7045470). The FET part and low temperature wafer bonding processes were done at Korea National Nanofab Center (NNFC, Daejeon, South Korea) and other post fabrication processes were executed at KIST Micro-Nano Fabrication Center (Seoul, South Korea).
Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/31
Y1 - 2017/10/31
N2 - In this paper, we present a full analytical model that can simulate an entire CMUT-FET structure with high accuracy and fast computation. Using the proposed analytical model, electromechanical properties, electrical characteristics (Id-Vg), and pressure sensitivity of the CMUT-FET are simulated and analyzed. The optimal bias point of the CMUT-FET is found to be 1.3 V (Sub-threshold operation), at which the calculated pressure sensitivity is 2.584 × 10-6 Pa-1. This optimum bias point is almost 11 times lower than 80 % pull-in voltage for conventional high-frequency CMUTs. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel-silicided source/drain junctions and low-temperature wafer bonding. The low-temperature wafer bonding successfully demonstrates the direct integration of CMUT on FET, which is verified via cross-sectional inspection. The fabrication technique is a promising solution and can be developed further to for integration with ICs.
AB - In this paper, we present a full analytical model that can simulate an entire CMUT-FET structure with high accuracy and fast computation. Using the proposed analytical model, electromechanical properties, electrical characteristics (Id-Vg), and pressure sensitivity of the CMUT-FET are simulated and analyzed. The optimal bias point of the CMUT-FET is found to be 1.3 V (Sub-threshold operation), at which the calculated pressure sensitivity is 2.584 × 10-6 Pa-1. This optimum bias point is almost 11 times lower than 80 % pull-in voltage for conventional high-frequency CMUTs. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel-silicided source/drain junctions and low-temperature wafer bonding. The low-temperature wafer bonding successfully demonstrates the direct integration of CMUT on FET, which is verified via cross-sectional inspection. The fabrication technique is a promising solution and can be developed further to for integration with ICs.
KW - Analytical model
KW - Field-effect transistor-embedded capacitive micromachined ultrasonic transducer (CMUT-FET)
KW - High-frequency operation
KW - Low-temperature wafer bonding
UR - http://www.scopus.com/inward/record.url?scp=85039435896&partnerID=8YFLogxK
U2 - 10.1109/ULTSYM.2017.8092012
DO - 10.1109/ULTSYM.2017.8092012
M3 - Conference contribution
AN - SCOPUS:85039435896
T3 - IEEE International Ultrasonics Symposium, IUS
BT - 2017 IEEE International Ultrasonics Symposium, IUS 2017
PB - IEEE Computer Society
T2 - 2017 IEEE International Ultrasonics Symposium, IUS 2017
Y2 - 6 September 2017 through 9 September 2017
ER -