Application of nanosphere lithography to charge trap flash memories with patterned Si ₃N ₄ trap layers

In this paper, nanosphere lithography (NSL) is applied to the surface of the Si ₃N ₄ trap layer in the charge trap flash device to improve its memory characteristics. A 500-nm-diameter polystyrene bead array was used as a mask to make patterns on the surface of the Si ₃N ₄ trap layer during etching processes using CF ₄ gases. The pattern depth measured by atomic force microscope was about 4 nm. The metal-aluminum oxide-nitride-oxide-silicon capacitor that has a patterned surface shows a larger capacitance-voltage memory window of 5 V, higher tunneling current at bias voltages higher than 10 V, and faster program speeds of 50 ms, as compared to those measured from the capacitor with the flat surface. These results are thought to be due to abundant memory traps available at the interface between the nitride and top oxide formed by NSL.