In this paper, nanosphere lithography (NSL) is applied to the surface of the Si 3N 4 trap layer in the charge trap flash device to improve its memory characteristics. A 500-nm-diameter polystyrene bead array was used as a mask to make patterns on the surface of the Si 3N 4 trap layer during etching processes using CF 4 gases. The pattern depth measured by atomic force microscope was about 4 nm. The metal-aluminum oxide-nitride-oxide-silicon capacitor that has a patterned surface shows a larger capacitance-voltage memory window of 5 V, higher tunneling current at bias voltages higher than 10 V, and faster program speeds of 50 ms, as compared to those measured from the capacitor with the flat surface. These results are thought to be due to abundant memory traps available at the interface between the nitride and top oxide formed by NSL.
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) Grants funded by the Korean Government (MEST) (2011-0028769). One of the authors (W.J. Cho) received a research Grant from Kwangwoon University in 2010.
- Charge trap flash
- Memory-trap density
- Nanosphere lithography
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering