TY - JOUR
T1 - Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture
AU - Nguyen Thi Huong, Giang
AU - Na, Yeoul
AU - Kim, Seon Wook
N1 - Funding Information:
This work was supported by the Korea University Research Grant, Seoul R&BD Program (10920), and the Basic Science Research Program through National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011-0010262).
PY - 2011/7
Y1 - 2011/7
N2 - A cross call between a host processor and FPGA is one of the main challenges for supporting automatic translation of high-level languages into hardware description languages (HDL). In this paper, we present a novel communication framework between the processor and FPGA, which supports unlimited cross calls and hardware recursive calls by following the software's frame layout in HDL code generation and sharing a stack space between software and hardware codes. Also, we introduce two implementation methods for our cross call, a direct and an indirect interfaces by an instruction-level and an interrupt communication, respectively. Our experiment shows that the proposed approach achieves our goal with small additional complexity in implementation and insignificant overhead in execution time.
AB - A cross call between a host processor and FPGA is one of the main challenges for supporting automatic translation of high-level languages into hardware description languages (HDL). In this paper, we present a novel communication framework between the processor and FPGA, which supports unlimited cross calls and hardware recursive calls by following the software's frame layout in HDL code generation and sharing a stack space between software and hardware codes. Also, we introduce two implementation methods for our cross call, a direct and an indirect interfaces by an instruction-level and an interrupt communication, respectively. Our experiment shows that the proposed approach achieves our goal with small additional complexity in implementation and insignificant overhead in execution time.
KW - CPU-FPGA communication interface
KW - CPU-FPGA cross call
KW - HLL-to-HDL translator
KW - Hardware-software co-design
UR - http://www.scopus.com/inward/record.url?scp=79956193755&partnerID=8YFLogxK
U2 - 10.1016/j.micpro.2011.03.005
DO - 10.1016/j.micpro.2011.03.005
M3 - Article
AN - SCOPUS:79956193755
SN - 0141-9331
VL - 35
SP - 462
EP - 472
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
IS - 5
ER -