Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture

Giang Nguyen Thi Huong, Yeoul Na, Seon Wook Kim

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


A cross call between a host processor and FPGA is one of the main challenges for supporting automatic translation of high-level languages into hardware description languages (HDL). In this paper, we present a novel communication framework between the processor and FPGA, which supports unlimited cross calls and hardware recursive calls by following the software's frame layout in HDL code generation and sharing a stack space between software and hardware codes. Also, we introduce two implementation methods for our cross call, a direct and an indirect interfaces by an instruction-level and an interrupt communication, respectively. Our experiment shows that the proposed approach achieves our goal with small additional complexity in implementation and insignificant overhead in execution time.

Original languageEnglish
Pages (from-to)462-472
Number of pages11
JournalMicroprocessors and Microsystems
Issue number5
Publication statusPublished - 2011 Jul

Bibliographical note

Funding Information:
This work was supported by the Korea University Research Grant, Seoul R&BD Program (10920), and the Basic Science Research Program through National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011-0010262).


  • CPU-FPGA communication interface
  • CPU-FPGA cross call
  • HLL-to-HDL translator
  • Hardware-software co-design

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence


Dive into the research topics of 'Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture'. Together they form a unique fingerprint.

Cite this