Architecting large-scale SRAM arrays with monolithic 3D integration

Joonho Kong; Young Ho Gong; Sung Woo Chung

doi:10.1109/ISLPED.2017.8009157

Architecting large-scale SRAM arrays with monolithic 3D integration

Joonho Kong, Young Ho Gong, Sung Woo Chung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: Tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs with M3D-based SRAM arrays lead to better performance and lower energy by 0.02%∼1.7% and 49.1%∼79.1%, respectively, compared to that with TSV-based 3D SRAM arrays.

Original language	English
Title of host publication	ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509060238
DOIs	https://doi.org/10.1109/ISLPED.2017.8009157
Publication status	Published - 2017 Aug 11
Event	22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan, Province of China Duration: 2017 Jul 24 → 2017 Jul 26

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
Country/Territory	Taiwan, Province of China
City	Taipei
Period	17/7/24 → 17/7/26

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This research was supported by NanoMaterial Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (No. 2015M3A7B7045470 and No. 2016M3A7B4910430). This research was also supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2015R1C1A1A01051836). We would also like to thank Prof. Sung Kyu Lim for discussion on M3D parameters and anonymous reviewers for their helpful feedback.

Publisher Copyright:
© 2017 IEEE.

Keywords

Energy
Last-Level Caches
Monolithic 3D Integrations
Performance

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/ISLPED.2017.8009157

Cite this

Kong, J., Gong, Y. H., & Chung, S. W. (2017). Architecting large-scale SRAM arrays with monolithic 3D integration. In ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design Article 8009157 (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISLPED.2017.8009157

Architecting large-scale SRAM arrays with monolithic 3D integration. / Kong, Joonho; Gong, Young Ho; Chung, Sung Woo.
ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2017. 8009157 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kong, J, Gong, YH & Chung, SW 2017, Architecting large-scale SRAM arrays with monolithic 3D integration. in ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design., 8009157, Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, Province of China, 17/7/24. https://doi.org/10.1109/ISLPED.2017.8009157

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abstract = "In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: Tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs with M3D-based SRAM arrays lead to better performance and lower energy by 0.02%∼1.7% and 49.1%∼79.1%, respectively, compared to that with TSV-based 3D SRAM arrays.",

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Architecting large-scale SRAM arrays with monolithic 3D integration

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