In this brief, we present a novel low area joint 2T spin orbit torque magnetic random access memory (SOT-MRAM) cell architecture. The proposed joint 2T cell achieves up to 15 % of SOT-MRAM cell area reduction by sharing the diffusion regions of transistors between adjacent cells. In addition, the small bit-line capacitance of the proposed SOT-MRAM can lead to 27% read energy reduction in comparison to the conventional SOT-MRAM. When the proposed 1 MB SOT-MRAM is used as L2 cache of X86 processor, the gem5 simulation results show the average of 18% dynamic energy savings in various workloads of SPEC2006 benchmarks.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2022 Mar 1|
Bibliographical notePublisher Copyright:
© 2004-2012 IEEE.
- Spin orbit torque magnetic random access memory (SOT-MRAM)
- memory cell area
- memory cell structure
- memory operation energy
ASJC Scopus subject areas
- Electrical and Electronic Engineering