Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing with Adjacent Cells

Yunho Jang; Jongsun Park

doi:10.1109/TCSII.2021.3126638

Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing with Adjacent Cells

Yunho Jang, Jongsun Park

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

In this brief, we present a novel low area joint 2T spin orbit torque magnetic random access memory (SOT-MRAM) cell architecture. The proposed joint 2T cell achieves up to 15 % of SOT-MRAM cell area reduction by sharing the diffusion regions of transistors between adjacent cells. In addition, the small bit-line capacitance of the proposed SOT-MRAM can lead to 27% read energy reduction in comparison to the conventional SOT-MRAM. When the proposed 1 MB SOT-MRAM is used as L2 cache of X86 processor, the gem5 simulation results show the average of 18% dynamic energy savings in various workloads of SPEC2006 benchmarks.

Original language	English
Pages (from-to)	1622-1626
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	69
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2021.3126638
Publication status	Published - 2022 Mar 1

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

Spin orbit torque magnetic random access memory (SOT-MRAM)
cache
memory cell area
memory cell structure
memory operation energy

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2021.3126638

Cite this

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title = "Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing with Adjacent Cells",

abstract = "In this brief, we present a novel low area joint 2T spin orbit torque magnetic random access memory (SOT-MRAM) cell architecture. The proposed joint 2T cell achieves up to 15 % of SOT-MRAM cell area reduction by sharing the diffusion regions of transistors between adjacent cells. In addition, the small bit-line capacitance of the proposed SOT-MRAM can lead to 27% read energy reduction in comparison to the conventional SOT-MRAM. When the proposed 1 MB SOT-MRAM is used as L2 cache of X86 processor, the gem5 simulation results show the average of 18% dynamic energy savings in various workloads of SPEC2006 benchmarks.",

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AB - In this brief, we present a novel low area joint 2T spin orbit torque magnetic random access memory (SOT-MRAM) cell architecture. The proposed joint 2T cell achieves up to 15 % of SOT-MRAM cell area reduction by sharing the diffusion regions of transistors between adjacent cells. In addition, the small bit-line capacitance of the proposed SOT-MRAM can lead to 27% read energy reduction in comparison to the conventional SOT-MRAM. When the proposed 1 MB SOT-MRAM is used as L2 cache of X86 processor, the gem5 simulation results show the average of 18% dynamic energy savings in various workloads of SPEC2006 benchmarks.

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Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing with Adjacent Cells

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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