Back biasing effects in tri-gate junctionless transistors

So Jeong Park; Dae Young Jeon; Laurent Montès; Sylvain Barraud; Gyu Tae Kim; Gérard Ghibaudo

doi:10.1016/j.sse.2013.06.004

Back biasing effects in tri-gate junctionless transistors

So Jeong Park, Dae Young Jeon, Laurent Montès, Sylvain Barraud, Gyu Tae Kim, Gérard Ghibaudo

Research output: Contribution to journal › Article › peer-review

30 Citations (Scopus)

Abstract

The back bias effect on tri-gate junctionless transistors (JLTs) has been investigated using experimental results and 2-D numerical simulations, compared to inversion-mode (IM) transistors. Results show that JLT devices are more sensitive to back biasing due to the bulk conduction. It is also shown that the effective mobility of JLT is significantly enhanced below flat band voltage by back bias. However, in extremely narrow JLTs, the back bias effect is suppressed by reduced portion of bulk conduction and strong sidewall gate controls. 2-D numerical charge simulation well supports experimental results by reconstructing the trend of back bias effects.

Original language	English
Pages (from-to)	74-79
Number of pages	6
Journal	Solid-State Electronics
Volume	87
DOIs	https://doi.org/10.1016/j.sse.2013.06.004
Publication status	Published - 2013

Bibliographical note

Funding Information:
This work was supported by European Union 7th Framework Program Project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology, Korea (Converging Research Center Program, 2012K001313, Global Frontier Research Program-the Center for Advanced Soft Electronics Code No. 2011-0031638) and the Korea Student Aid Foundation (KOSAF) grant funded by the Korea Government (MEST) (No. S2-2009-000-00991-1 ).

Keywords

2-D numerical simulation
Back bias effect
Channel width variation
Junctionless transistor
SOI (silicon on insulator)

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1016/j.sse.2013.06.004

Cite this

@article{a23a4456fa5742abbbd210ef84a8a1d1,

title = "Back biasing effects in tri-gate junctionless transistors",

abstract = "The back bias effect on tri-gate junctionless transistors (JLTs) has been investigated using experimental results and 2-D numerical simulations, compared to inversion-mode (IM) transistors. Results show that JLT devices are more sensitive to back biasing due to the bulk conduction. It is also shown that the effective mobility of JLT is significantly enhanced below flat band voltage by back bias. However, in extremely narrow JLTs, the back bias effect is suppressed by reduced portion of bulk conduction and strong sidewall gate controls. 2-D numerical charge simulation well supports experimental results by reconstructing the trend of back bias effects.",

keywords = "2-D numerical simulation, Back bias effect, Channel width variation, Junctionless transistor, SOI (silicon on insulator)",

author = "Park, {So Jeong} and Jeon, {Dae Young} and Laurent Mont{\`e}s and Sylvain Barraud and Kim, {Gyu Tae} and G{\'e}rard Ghibaudo",

note = "Funding Information: This work was supported by European Union 7th Framework Program Project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology, Korea (Converging Research Center Program, 2012K001313, Global Frontier Research Program-the Center for Advanced Soft Electronics Code No. 2011-0031638) and the Korea Student Aid Foundation (KOSAF) grant funded by the Korea Government (MEST) (No. S2-2009-000-00991-1 ).",

year = "2013",

doi = "10.1016/j.sse.2013.06.004",

language = "English",

volume = "87",

pages = "74--79",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Ltd",

}

TY - JOUR

T1 - Back biasing effects in tri-gate junctionless transistors

AU - Park, So Jeong

AU - Jeon, Dae Young

AU - Montès, Laurent

AU - Barraud, Sylvain

AU - Kim, Gyu Tae

AU - Ghibaudo, Gérard

N1 - Funding Information: This work was supported by European Union 7th Framework Program Project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology, Korea (Converging Research Center Program, 2012K001313, Global Frontier Research Program-the Center for Advanced Soft Electronics Code No. 2011-0031638) and the Korea Student Aid Foundation (KOSAF) grant funded by the Korea Government (MEST) (No. S2-2009-000-00991-1 ).

PY - 2013

Y1 - 2013

N2 - The back bias effect on tri-gate junctionless transistors (JLTs) has been investigated using experimental results and 2-D numerical simulations, compared to inversion-mode (IM) transistors. Results show that JLT devices are more sensitive to back biasing due to the bulk conduction. It is also shown that the effective mobility of JLT is significantly enhanced below flat band voltage by back bias. However, in extremely narrow JLTs, the back bias effect is suppressed by reduced portion of bulk conduction and strong sidewall gate controls. 2-D numerical charge simulation well supports experimental results by reconstructing the trend of back bias effects.

AB - The back bias effect on tri-gate junctionless transistors (JLTs) has been investigated using experimental results and 2-D numerical simulations, compared to inversion-mode (IM) transistors. Results show that JLT devices are more sensitive to back biasing due to the bulk conduction. It is also shown that the effective mobility of JLT is significantly enhanced below flat band voltage by back bias. However, in extremely narrow JLTs, the back bias effect is suppressed by reduced portion of bulk conduction and strong sidewall gate controls. 2-D numerical charge simulation well supports experimental results by reconstructing the trend of back bias effects.

KW - 2-D numerical simulation

KW - Back bias effect

KW - Channel width variation

KW - Junctionless transistor

KW - SOI (silicon on insulator)

UR - http://www.scopus.com/inward/record.url?scp=84879809146&partnerID=8YFLogxK

U2 - 10.1016/j.sse.2013.06.004

DO - 10.1016/j.sse.2013.06.004

M3 - Article

AN - SCOPUS:84879809146

SN - 0038-1101

VL - 87

SP - 74

EP - 79

JO - Solid-State Electronics

JF - Solid-State Electronics

ER -

Back biasing effects in tri-gate junctionless transistors

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this