Abstract
The back bias effect on tri-gate junctionless transistors (JLTs) has been investigated using experimental results and 2-D numerical simulations, compared to inversion-mode (IM) transistors. Results show that JLT devices are more sensitive to back biasing due to the bulk conduction. It is also shown that the effective mobility of JLT is significantly enhanced below flat band voltage by back bias. However, in extremely narrow JLTs, the back bias effect is suppressed by reduced portion of bulk conduction and strong sidewall gate controls. 2-D numerical charge simulation well supports experimental results by reconstructing the trend of back bias effects.
Original language | English |
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Pages (from-to) | 74-79 |
Number of pages | 6 |
Journal | Solid-State Electronics |
Volume | 87 |
DOIs | |
Publication status | Published - 2013 |
Bibliographical note
Funding Information:This work was supported by European Union 7th Framework Program Project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology, Korea (Converging Research Center Program, 2012K001313, Global Frontier Research Program-the Center for Advanced Soft Electronics Code No. 2011-0031638) and the Korea Student Aid Foundation (KOSAF) grant funded by the Korea Government (MEST) (No. S2-2009-000-00991-1 ).
Keywords
- 2-D numerical simulation
- Back bias effect
- Channel width variation
- Junctionless transistor
- SOI (silicon on insulator)
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry