― As static random access memory (SRAM) takes a dominant portion in current system on a chip (SoC), lowering the supply voltage of SRAM would effectively reduce the overall power consumption of SoC. However, lowering SRAM supply voltage causes large read delays and malfunctions. In this paper, we present a bit-line (BL) decoupled SRAM structure that can efficiently provide fast and accurate read operation in near threshold voltage operations. The improvement in read operation is obtained by reducing bit-line parasitic capacitance with decoupling between bit-line and data node in memory cell in the proposed SRAM. The BL decoupled SRAM implementation using 28nm CMOS process shows that the average and standard deviation of read delay are reduced by 40.8% and 56.3%, respectively, compared to conventional SRAM under 0.5 V.
|Title of host publication||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2022|
|Event||19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of|
Duration: 2022 Oct 19 → 2022 Oct 22
|Name||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Conference||19th International System-on-Chip Design Conference, ISOCC 2022|
|Country/Territory||Korea, Republic of|
|Period||22/10/19 → 22/10/22|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (NRF-2020M3F3A2A01082591). The EDA tool was supported by the IC Design Education Center(IDEC), Korea.
© 2022 IEEE.
- Low Power Embedded Memory
- Near Threshold Voltage
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Science Applications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality