Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations

Hyunchul Park; Jongsun Park

doi:10.1109/ISOCC56007.2022.10031354

Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations

Hyunchul Park, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

― As static random access memory (SRAM) takes a dominant portion in current system on a chip (SoC), lowering the supply voltage of SRAM would effectively reduce the overall power consumption of SoC. However, lowering SRAM supply voltage causes large read delays and malfunctions. In this paper, we present a bit-line (BL) decoupled SRAM structure that can efficiently provide fast and accurate read operation in near threshold voltage operations. The improvement in read operation is obtained by reducing bit-line parasitic capacitance with decoupling between bit-line and data node in memory cell in the proposed SRAM. The BL decoupled SRAM implementation using 28nm CMOS process shows that the average and standard deviation of read delay are reduced by 40.8% and 56.3%, respectively, compared to conventional SRAM under 0.5 V.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	7-8
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031354
Publication status	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 2022 Oct 19 → 2022 Oct 22

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	22/10/19 → 22/10/22

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported by National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (NRF-2020M3F3A2A01082591). The EDA tool was supported by the IC Design Education Center(IDEC), Korea.

Publisher Copyright:
© 2022 IEEE.

Keywords

Low Power Embedded Memory
Near Threshold Voltage
SRAM

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Hardware and Architecture
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISOCC56007.2022.10031354

Cite this

Park, H., & Park, J. (2022). Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations. In Proceedings - International SoC Design Conference 2022, ISOCC 2022 (pp. 7-8). (Proceedings - International SoC Design Conference 2022, ISOCC 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC56007.2022.10031354

Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations. / Park, Hyunchul; Park, Jongsun.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 7-8 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, H & Park, J 2022, Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 7-8, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 22/10/19. https://doi.org/10.1109/ISOCC56007.2022.10031354

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abstract = "― As static random access memory (SRAM) takes a dominant portion in current system on a chip (SoC), lowering the supply voltage of SRAM would effectively reduce the overall power consumption of SoC. However, lowering SRAM supply voltage causes large read delays and malfunctions. In this paper, we present a bit-line (BL) decoupled SRAM structure that can efficiently provide fast and accurate read operation in near threshold voltage operations. The improvement in read operation is obtained by reducing bit-line parasitic capacitance with decoupling between bit-line and data node in memory cell in the proposed SRAM. The BL decoupled SRAM implementation using 28nm CMOS process shows that the average and standard deviation of read delay are reduced by 40.8% and 56.3%, respectively, compared to conventional SRAM under 0.5 V.",

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note = "Funding Information: ACKNOWLEDGMENT This work was supported by National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (NRF-2020M3F3A2A01082591). The EDA tool was supported by the IC Design Education Center(IDEC), Korea. Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",

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doi = "10.1109/ISOCC56007.2022.10031354",

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N2 - ― As static random access memory (SRAM) takes a dominant portion in current system on a chip (SoC), lowering the supply voltage of SRAM would effectively reduce the overall power consumption of SoC. However, lowering SRAM supply voltage causes large read delays and malfunctions. In this paper, we present a bit-line (BL) decoupled SRAM structure that can efficiently provide fast and accurate read operation in near threshold voltage operations. The improvement in read operation is obtained by reducing bit-line parasitic capacitance with decoupling between bit-line and data node in memory cell in the proposed SRAM. The BL decoupled SRAM implementation using 28nm CMOS process shows that the average and standard deviation of read delay are reduced by 40.8% and 56.3%, respectively, compared to conventional SRAM under 0.5 V.

AB - ― As static random access memory (SRAM) takes a dominant portion in current system on a chip (SoC), lowering the supply voltage of SRAM would effectively reduce the overall power consumption of SoC. However, lowering SRAM supply voltage causes large read delays and malfunctions. In this paper, we present a bit-line (BL) decoupled SRAM structure that can efficiently provide fast and accurate read operation in near threshold voltage operations. The improvement in read operation is obtained by reducing bit-line parasitic capacitance with decoupling between bit-line and data node in memory cell in the proposed SRAM. The BL decoupled SRAM implementation using 28nm CMOS process shows that the average and standard deviation of read delay are reduced by 40.8% and 56.3%, respectively, compared to conventional SRAM under 0.5 V.

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Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations

Abstract

Publication series

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Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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